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Upcasting (2)

VHDL Testbench (2)

Vacuity (2)

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Verification Cycles (2)

Vertical Reuse (2)

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March 2020

An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Vishal Patel, Manoj Pandey - Arastu Systems Article
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Verification IP Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic Article
Formal Verification of RISC-V® Processors
Formal Verification Mar 01, 2020 Dr. Ashish Darbari Article

January 2020

Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
Standards Jan 07, 2020 Matthew Ballance Article
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Standards Jan 07, 2020 Joe Hupcey Article
Low Power Coverage: The Missing Piece in Dynamic Simulation
Simulation Jan 07, 2020 Progyna Khondkar Article
Low Power Apps: Shaping the Future of Low Power Verification
Standards Jan 07, 2020 Verification News Article
Effective Elements List and Transitive Natures of UPF Commands
Standards Jan 07, 2020 Progyna Khondkar Article
Managing and Automating HW/SW Tests from IP to SoC
Simulation Jan 07, 2020 Matthew Ballance Article
Reusable UPF: Transitioning from RTL to Gate Level Verification
Standards Jan 07, 2020 Verification News Article
Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy
Standards Jan 07, 2020 Matthew Ballance Article
Results Checking Strategies with Portable Stimulus
Standards Jan 07, 2020 Matthew Ballance Article
Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
Standards Jan 07, 2020 Verification News Article
Coverage Driven Verification of NVMe Using Questa VIP
Simulation Jan 07, 2020 Verification News Article
Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task
Functional Safety Jan 07, 2020 Charles Battikha Article
Technical Paper: Push-Button FMEDAs for Automotive Safety - Automating a Tedious Task
Functional Safety Jan 07, 2020 pdf

December 2019

Achieving Functional Safety for Autonomous Vehicle SoC Designs
Functional Safety Dec 06, 2019 Jake Wiltgen Article
Technical Paper: Achieving Functional Safety for Autonomous Vehicle SoC Designs
Functional Safety Dec 06, 2019 pdf
Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
Acceleration Dec 03, 2019 Jean-Marie Brunet Article
Deadlock Prevention Made Easy with Formal Verification
Formal Verification Dec 03, 2019 Dr. Jeremy Levitt Article
Exercising State Machines with Command Sequences
Portable Stimulus Dec 03, 2019 Matthew Ballance Article
Designing A Portable Stimulus Reuse Strategy
Portable Stimulus Dec 03, 2019 Matthew Ballance Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing Dec 03, 2019 Kurt Takara Article

November 2019

UVMC 2.3.2 Library
UVMC Nov 15, 2019 html
UVM Connect 2.3.2 Kit
UVMC Nov 14, 2019 John Stickley tar

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

UALink VIP Webinar

Wednesday, Oct 15th-10:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

DVCon Europe 2025

October 14th - 15th | Munich, Germany

osmosis Europe 2025

October 16th | Munich, Germany

RISC-V Summit 2025

October 22nd - 23rd | Santa Clara, CA

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

Portable Stimulus Webinar

Wednesday, Oct 29th-10:00 AM PDT

Portable Stimulus: What can it do for me? | Presented by Doulos

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

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