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Show Less

February 2016

Component Configuration
Planning, Measurement and Analysis Feb 12, 2016 Harry Foster pdf
Dual Domain Hierarchy Pattern
Planning, Measurement and Analysis Feb 12, 2016 Harry Foster pdf

December 2015

Precedence Chain Property
Planning, Measurement and Analysis Dec 22, 2015 Harry Foster pdf
Response Chain Property
Planning, Measurement and Analysis Dec 22, 2015 Harry Foster pdf
Response Property
Planning, Measurement and Analysis Dec 21, 2015 Harry Foster pdf
Precedence Property
Planning, Measurement and Analysis Dec 21, 2015 Harry Foster pdf
Universality Property
Planning, Measurement and Analysis Dec 21, 2015 Harry Foster pdf
Bounded Existence Property
Planning, Measurement and Analysis Dec 21, 2015 Harry Foster pdf
Existence Property
Planning, Measurement and Analysis Dec 21, 2015 Harry Foster pdf
Absence Property
Planning, Measurement and Analysis Dec 18, 2015 Harry Foster pdf
Layering Sequence
Planning, Measurement and Analysis Dec 18, 2015 Harry Foster pdf
Utility
Planning, Measurement and Analysis Dec 18, 2015 Harry Foster pdf
Façade
Planning, Measurement and Analysis Dec 18, 2015 Harry Foster pdf
BFM-Proxy Pair
Planning, Measurement and Analysis Dec 18, 2015 Harry Foster pdf

November 2015

UVM Framework: Create a UVM Environment in Less than an Hour
UVM Framework Nov 25, 2015 Bob Oden Webinar
UVM Framework: Create a UVM Environment in Less than an Hour
UVM Framework Nov 25, 2015 Bob Oden pdf
Creating UVM Testbenches for Simulation & Emulation Platform Portability
Acceleration Nov 24, 2015 Hans Van Der Schoot pdf

June 2015

Unit Testing Your Way to a Reliable Testbench
Simulation Jun 06, 2015 Neil Johnson Article
UVM Debug? Beyond Logfiles
UVM - Universal Verification Methodology Jun 01, 2015 Rich Edelman Session
UVM Debug? Beyond Logfiles
UVM - Universal Verification Methodology Jun 01, 2015 Rich Edelman pdf

March 2015

UVM Rapid Adoption: A Practical Subset of UVM
UVM - Universal Verification Methodology Mar 31, 2015 Tom Fitzpatrick Conference
Are You Smarter Than Your Testbench? With a Little Work You Can Be
UVM - Universal Verification Methodology Mar 03, 2015 Rich Edelman Paper
Are You Smarter Than Your Testbench? With a Little Work You Can Be
UVM - Universal Verification Methodology Mar 03, 2015 Rich Edelman pdf
UVM Sans UVM: An Approach to Automating UVM Testbench Writing
UVM - Universal Verification Methodology Mar 02, 2015 Rich Edelman pdf
UVM Sans UVM: An Approach to Automating UVM Testbench Writing
UVM - Universal Verification Methodology Mar 02, 2015 Rich Edelman Paper

Agentic AI Webinar

Wednesday, Apr 22nd-8:00 AM PDT

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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