No RTL Yet? No Problem: UVM Testing a SystemVerilog Fabric Model

Building a UVM¹ testbench is a hard job, made harder when operational RTL is not yet available to test. SystemVerilog² is a powerful modeling language that can be used to build a high-level model of hardware before RTL is available. This model is fast to write and can be as functionally complete as needed. This article will describe the creation and use of a fabric model to build and bring up a testbench. When the RTL is available it can be plugged into the testbench model with little change required.

The main contributions of this article are showing a fully functional model of a medium complexity communication fabric; writing the model using SystemVerilog; and building a reusable testbench that can support block testing as well as support system level tests.

The Fabric

The fabric is a simple two port switch with buffering. Each communication pathway contains 5 channels. Each channel is a Ready/Valid channel with similarities to an AMBA® AXI³ channel. The fabric supports multiple outstanding transactions, pipelining and large burst data transfers. It also supports traffic priority (quality of service). This is the model. It is written using SystemVerilog.

Associative arrays are used to manage out-of-order transactions. Queues and dynamic arrays are used for managing lists. Classes are used to hold the transferred information - a class each for RA (Read Address), WA (Write Address), RD (Read Data), WD (Write Data) and B (Write Response), respectively. Packed structs are used for managing the tag bit fields.

The Testbench

The testbench is built to test the features supported by the fabric. It is a basic block testbench, testing transfer, buffering limits and other edge conditions in the RTL. This testbench will also be reusable to the system tests. The testbench is a basic UVM testbench with transfer sequences and background traffic sequences available.

The DUT

The actual device under test will be two fabrics connected together.

Background

The RTL implements an AXI-like fabric. It is a simple fabric (simpler than AMBA® AXITM), but has support for quality of service, out-of-order completion, and other high-end features. The verification team wishes to get an early start on verification of this fabric. But early, functional RTL is not available. In order for the verification team to get an early start on the verification environment, having an early model of the DUT is desirable.

In this article, a theoretical verification team has built a UVM testbench and needs to make sure that the testbench can check and verify the hardware. The tests are quite simple – generating streams of READs and WRITEs. This theoretical verification team is testing a simple AXI-like fabric (it is not an AXI system). The fabric is a simple two port switch as seen in Figure 1. The system under test connects two of these fabrics.

^{Figure 1: Simple two port switch}