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Simulation Nov 19, 2025 John Liu - Northrop Grumman pdf
Don't Let VHDL Debugging Slow You Down! Use Questa One Sim
Simulation Nov 12, 2025 Nicole Munson pdf
Introducing BUGGED OUT — A new bite-sized podcast for verification engineers
Planning, Measurement and Analysis Nov 10, 2025 Harry Foster link
HLV: Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Nov 05, 2025 Vlada Kalinic pdf

October 2025

Improving Verification Productivity Using Questa One Sim
Simulation Oct 23, 2025 Karim Ameziane pdf
Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Machine Learning Oct 16, 2025 Zvi Ben Yosef - Nextsilicon mp4
Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Machine Learning Oct 16, 2025 Zvi Ben Yosef - Nextsilicon pdf
Combining Performance and Formal Security Guarantees for Hardware Accelerators
Formal Verification Oct 16, 2025 Lucas Deutschmann - Rptu University Kaiserslautern-Landau pdf
Combining Performance and Formal Security Guarantees for Hardware Accelerators
Formal Verification Oct 16, 2025 Lucas Deutschmann - Rptu University Kaiserslautern-Landau mp4
New RTL Modeling Constructs in Verilog
Simulation Oct 16, 2025 Dave Rich link
Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Machine Learning Oct 16, 2025 Tobias Ludwig - Lubis Eda pdf
Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Machine Learning Oct 16, 2025 Tobias Ludwig - Lubis Eda mp4
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Formal Verification Oct 16, 2025 Bryan Olmos - Infineon mp4
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Formal Verification Oct 16, 2025 Bryan Olmos - Infineon pdf
Formally Verifying Security Properties of CHERI Hardware and Software
Formal Verification Oct 16, 2025 Thomas Bauereiss - University Of Cambridge mp3
Formally Verifying Security Properties of CHERI Hardware and Software
Formal Verification Oct 16, 2025 Thomas Bauereiss - University Of Cambridge pdf
Harnessing AI for Real-world Hardware Verification
Machine Learning Oct 16, 2025 Matthew Taylor - Doulos pdf
Harnessing AI for Real-world Hardware Verification
Machine Learning Oct 16, 2025 Matthew Taylor - Doulos mp4
Stimulus Free Verification of a Clock Bridge Using Static and Formal
Formal Verification Oct 16, 2025 Kanthi Palaniappan - Nokia mp4
Stimulus Free Verification of a Clock Bridge Using Static and Formal
Formal Verification Oct 16, 2025 Kanthi Palaniappan - Nokia pdf
Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP
Verification IP Oct 15, 2025 Justin Bunnell pdf
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
Questa Design Solutions Oct 08, 2025 Kirolos Magdy pdf
Interchange Format Standard in Hierarchical CDC and RDC Analysis
Reset-Domain Crossing Oct 06, 2025 Farhad Ahmed link
Did You Know QuestaSim Supports VHDL-2019?
Simulation Oct 01, 2025 Abdelrahman Tharwat pdf

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

VA Live El Segundo

Tuesday, Feb 24th-9:30 AM PST

Discussing the latest advancements in RTL simulation.

FPU Verification Webinar

Wednesday, Feb 25th-8:00 AM PST

AI Assisted FPU Verification Using Questa One SFV

DVCon US 2026

March 2nd – 5th, 2026 | Hyatt Regency, Santa Clara

Verification IP Webinar

Wednesday, Mar 11th-8:00 AM PDT

Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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