Handling Reset-Domain Crossing (RDC) for Designs with Set-Reset Flops

Introduction

Reset-Domain Crossing:
Reset-domain crossing (RDC) is a structure in digital design where a signal generated by a flip-flop using an asynchronous reset (or set) is captured by another flop using another asynchronous reset (or set).

^{Figure 1: Basic RDC (Reset-Domain Crossing).}

Every reset signal in a digital design, which can assert asynchronously and independently of any clock, is called as “Asynchronous reset”. All flops using same asynchronous reset in a digital design corresponds to a “Reset domain”. So, if signal generated by a flop in one reset domain is captured by a flop in another reset domain, such structures are called “Reset Domain Crossings”. The transmitting flop is called Tx flop and the receiving flop is referred to as Rx flop. Further, reset (or set) driving the Tx flop is called tx_rst (or tx_set) and reset (or set) driving the Rx flop is called rx_rst (or rx_set).

This can be problematic because an asynchronous reset assertion on the Rx flop can occur asynchronous to the Rx clock, resulting in metastability or data loss. Suppose both flops are using the same clock and the Tx flop launches at the positive edge of clock, an asynchronous rx_rst at same time can force the Rx flop to a conflicting value at same time, forcing the flop into metastability or incorrect data capture.

The problem becomes more complex when set-reset flop comes into picture. A set-reset flop, in the context of this paper, is a flip-flop with two asynchronous set/reset (Figure 2). With more than one reset on a single flop, the problem becomes more complex. Although designers are taught to avoid such structures in designs, various design scenarios can still end-up with RTL code which can get synthesized as a set/reset flop. Often in large design teams, engineers or teams responsible for RDC cleanup of the design are different from the RTL coders. And with tight design schedules and RDC happening late in the RTL closure stage, it is becoming very difficult to avoid such design structures. This structure is hence expected to be caught by the RDC EDA tools and have to be analyzed and fixed by the RDC engineer.

^{Figure 2. Basic SR flop with active_high priority set and active_low secondary reset.}

As per our experience, we have seen that most common usage of set-reset flop is as shown in example above in Figure 2. As possible in RTL code, this set-reset flop can have many variations (Table 1) based on edge sensitivity of both resets involved and the value forced by these resets. For simplicity, if the value forced is binary 1, we will call it a set, and if the value forced to binary ‘0’, we would call it a reset. Also, you can also see that in the RTL code in Figure 2 above suggest that one reset has priority over another based on the if-else conditional hierarchy.

In this paper, we will assume all sets and resets as asynchronous. Cases covering one or both of resets being synchronous are kept out of the scope of paper and can be considered for future work. We will also assume that one set/reset is always having priority over another as shown in the example above. We have also kept non-resettable flops out of the purview of this paper.

• We will use following nomenclature moving forward.
• In general, a flop with two resets will be called a set-reset flop or SR flop in short.
• A reset signal forcing the flop to binary ‘1’ will be called as ‘set’
• A reset signal forcing the flop to binary ‘0’ will be called as ‘reset’ or ‘rst’ in short.
• The reset having priority over another in if-else tree will be considered ‘priority set’ or ‘priority reset’ depending upon the output.
• The reset having lower priority another in if-else tree will be considered ‘secondary set’ or ‘secondary reset’ depending upon the output.
• In general, a wire will be called ‘reset’ as a generic term if used in a flop to force a specific constant value.

As discussed above, theoretically we can have several variations of set-reset flop with difference in edge sensitivity of resets, value forced at output of flop and also priority.