Reset-Domain Crossing

Reset-Domain Crossing (RDC) Overview

Complex SoCs, like designs from automobile or aerospace industry, not only involve multiple clock domains, but even more complex reset architectures leading to many RDC domains. Resets are important part of any design as these lead a design to a known state. Designs involving functional safety may have many independent reset signals which may be used to reset selectively a part of the design, while rest of the design may be in the functional mode. This will lead to interactions between reset signals and data signals across reset domain boundaries. RDC signals can lead to functional issues and thus should be caught early in the design cycle.

The transmission of data across sequential elements that are reset by different asynchronous and soft reset domains can cause reset domain crossing (RDC) paths, which can lead to metastability. This metastability can cause unpredictable values to be propagated to down-stream logic and prevent a design from functioning normally. A proper reset domain crossing sign-off methodology is required to avoid metastability and other functional problems in chip designs.

Note that this meta-stability is different from the one which may occur due to clock domain crossing. So even if you have proper synchronization of a clock domain crossing between transmitter and receiver, it may still cause meta-stability due to asynchronous reset at transmitter which is in different reset domain from asynchronous reset at receiver.

RDC synchronizers are quite flexible and may not have standard structure like CDC Synchronizers of DMUX, FIFO and Handshake type. Simply timing the Reset assertion at transmitter side w.r.t. reset assertion at receiver is sufficient for isolating the RDC issue. Other ways are to block the Data transfer from Tx flop to Rx flop or clock path of the Receiver flop. All these checks are performed during RDC verification by the design team or the verification team.

Challenges and Considerations

Since the RDC synchronizers are flexible in nature, without any standard synchronizer structure, it becomes more crucial to ensure the design assumptions are correct through some advance technique in your RDC verification methodology for accurate and efficient analysis. This includes the protocol checking of design assumptions, better constraining or reducing the false reporting of RDCs.

Static verification tools often come with standard methodologies and goals for RDC verification. But improper constraints, assumptions and configurations in RDC analysis can lead to huge number of violations which are nothing but noise in the static analysis. For false violations verification engineers apply waivers. This adds to another burden of waiver management. It is often desired that the tools should have a methodology which has an automated data analysis or machine learning solution which can detect the issues in the setup and give corrective suggestions to verification engineers to eliminate noise.

Integrating RDC verification into the overall verification flow of a digital design poses challenges in terms of tool compatibility, data exchange, and coordination with other verification tasks such as functional verification and timing analysis. Addressing these challenges requires a combination of advanced verification techniques, comprehensive tool support, rigorous design practices, and domain expertise. By overcoming these challenges, designers can ensure the reliable operation of digital circuits, particularly in safety-critical applications where RDC issues can have severe consequences.

Reset-Domain Crossing (RDC) Conclusion

Reset-domain crossing (RDC) verification is no more a good to have kind of verification for designs with asynchronous resets, even if they are not high in number. There is a risk of Silicon failure due to meta-stability introduced for RDC, even if CDC verification is closed for the design, until you perform the RDC analysis. So RDC verification is a critical aspect of the digital design to ensure the reliable operation of the complex modern SoCs with asynchronous nature of reset signals.

A robust verification methodology is required for the exhaustive RDC analysis to catch the meta-stability issues early in the design cycle and mitigate the risks.