Analog Mixed-Signal Verification
Today’s ICs increasingly rely on complex mixed-signal functionality with stringent performance and low power requirements for applications in segments including IoT, Automotive, Communications, and Industrials. Verification of these complex mixed-signal ICs is challenging due to the need to ensure that they meet demanding specifications with correct connectivity, functionality, and adequate system performance across analog/digital (A/D) interfaces on the chip.
To address these challenges, verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the sub-system level. These mixed-signal simulation solutions need to be fast, accurate, easy to use, and seamlessly integrate into existing analog and digital verification flows.
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Analog/Mixed-Signal Verification (AMS) Tracks
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Improve AMS Verification Quality
This track introduces methodologies available in AMS design environments that could help quantify the quality of the Analog/Mixed-Signal (AMS) verification process. Understanding these approaches, will help learn how to properly address the various issues and problems in AMS verification process, thus, help improve the overall process Quality. -
Improve AMS Verification Performance
This track will introduce various modeling practices available in an Analog/Mixed-Signal (AMS) design environment to help understand how to efficiently utilize them. Understanding the modeling tools available in AMS domain, will help learn how to properly address them, thus, help improve the AMS verification performance. -
AMS Design Configuration Schemes
This track will introduce the various techniques available in Analog/Mixed-Signal (AMS) design environment to help understand how to efficiently utilize them. Understanding the challenges in AMS verification, will help learn how to properly address them, thus, creating an efficient design environment.
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Analog/Mixed-Signal Verification (AMS) Forum Discussion
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What happens when there is a simultaneous Read and Write launched to the same address in AXI4?
Sep 12, 2024 SystemVerilog -
Is there a standard way to include temperature dependence in systemVerilog?
Jul 01, 2022 SystemVerilog