Router scoreboard implementation

SystemVerilog
,
1

Router Scoreboard Implementation;

  1. The router takes 2 input streams of containing a 32bit payload and 4bit .
  2. The is a bitmap indicating which output port the input payload should be routed to.
    Multiple dst bits can be set in one .
  3. One payload message will be forwarded to destination output interface with 32bit payload divided into 4 transactions in LSB to MSB order.
    Assumptions:
  4. The input/output interfaces are vld‑rdy.
  5. The monitors have been implemented to report input/output transactions

====================

my run_phase will look like this;

task run_phase(uvm_phase phase);

fork

  process_input_port(0);
  process_input_port(1);

  process_output_port(0);
  process_output_port(1);
  process_output_port(2);
  process_output_port(3);

join

endtask

//-----------approach_1
regular, simple approach.
wait for queuesize to become non-zero and then pop_out element
the problem here is : we are taking T amount of time to begin comparision
what in case if already first byte appeared from DUT before this and
when we start comparing, it is the actual second byte from DUT,
oveall the first byte from the DUT appeared so quickly, comparision will
still fails

task process_output_port(int port_num);

output_trans out_tx;

bit [7:0] exp_byte;
bit [7:0] act_byte;

forever begin

  out_fifo[port_num].get(out_tx);

  act_byte = out_tx.beat_msg;

  wait(expected_q[port_num].size()>0);

  // Peek expected byte
  exp_byte = expected_q[port_num][0];

  // Compare
  if(act_byte !== exp_byte) begin

    `uvm_error("SCOREBOARD",
      $sformatf(
        "OUT%0d MISMATCH EXP=%0h ACT=%0h",
    // No pop on mismatch

  end
  else begin

    `uvm_info("SCOREBOARD PASS",
    // Pop only after successful compare
    void'(expected_q[port_num].pop_front());
  end
end
endtask

//-----------approach_2
in this approach, DUT generated data first, but at this moment, predictor has no expected data hence reporting as uvm_error
I preferred this approach becaue, the first or any byte of data could be unwanted or invalid or junk data, so wanted to ignore this.
But still, problem here is, we can see many number of uvm_error when quuesize is zero,
it is like FAKE error

task process_output_port(int port_num);

output_trans out_tx;

bit [7:0] exp_byte;
bit [7:0] act_byte;

forever begin

  out_fifo[port_num].get(out_tx);

  act_byte = out_tx.beat_msg;

  // DUT generated data but predictor has no expected data
  if(expected_q[port_num].size() == 0) begin

    `uvm_error("SCOREBOARD",
      $sformatf(
        "No expected data for OUT%0d, ACT=%0h",
         port_num,
         act_byte))
    continue;
  end

  // Peek expected byte
  exp_byte = expected_q[port_num][0];

  // Compare
  if(act_byte !== exp_byte) begin

    `uvm_error("SCOREBOARD",
      $sformatf(
        "OUT%0d MISMATCH EXP=%0h ACT=%0h",
    // No pop on mismatch

  end
  else begin

    `uvm_info("SCOREBOARD PASS",
    // Pop only after successful compare
    void'(expected_q[port_num].pop_front());
  end
end
endtask

So with both approaches also, I have difficulties,

What is the solution for this kind of implementation, please suggest.

So scoreobard should ensure that it handles, timing between input and output like

input can appear too early or too late

input can appear too early or too late

Is this the role of scoreboard or monitor should take care of this along with sending valid/invalid/junk data.

Kindly suggest, what to be taken care in scoreboard?