Hi … I have doubts about the independence of write/read channels.
Single master issues a valid Read and Write transaction to the same address with different IDs simultaneously[single master and single slave]. which transaction will occur first and how?
This link seems to address your question.
You would likely get a better answer on an ARM specific forum.
Hi… Based on the link, I understand that we can’t send simultaneous read and write. the master must wait for a response to the first transaction before issuing the second transaction for the same address access.
please confirm my understanding.
I don’t think the ARM standard explicitly states the required behavior here. Read and Write channels are independent. I could see an argument for both cases - the slave device could do either.
@amsaveni.c Pending reads for completion of any writes is something that many folks would do in there master side AXI design, however I don’t think this is required by any standard.