SystemVerilog property with a real datatype input argument

SystemVerilog
1

I am currently working on an AMS verification project for a switching regulator. I’ve written an interface to average out the output voltage ripple seen on a given signal. I’d like to add a suite of asserts on these to automate my checkers and I’ve run into some questions.

I’m aware that I can include real data types within a property, but I’d like to reduce the amount of retyping I have to do and include a real datatype as an input argument to a property.

this one compiles cleanly


import math_functions_pkg::*;  //get abs function
interface signal_chk_intf(input bit clk);
   real signal; //input signal
   real signal_q[$];  //q to hold the input signal
   int num_samples = 1000; //number of samples to hold in my rolling buffer. 
   average = 0; 
  
   real expected_dc_val; //expected target value
   real dc_tol;          //dc tolerance 
   real ripple_tol;      //allowed ripple tolerance 
   
   
   clocking cb(@posedge clk);
      default input#(1step);
      input signal;
   endclocking 

  always @(cb) begin
    //stuff to fill up the queue and calculate the average
    //this part of my code already works
  end 

  property dc_tol_chk(bit disable_chk);
    @(cb) disable(iff(disable_chk) abs(average-expected_dc_val) <= dc_tol); 
  endproperty 
  
  my_dc_tol_chk: assert(dc_tol_chk) else `uvm_error(...) 

  property ripple_tol_chk(bit disable_chk);
    @(cb)disable(iff(disable_chk) signal_q.max()-signal_q.min() <= ripple_tol; 
 //some assumptions being made that signal_q.max/min would eventaully catch the edges of the ripple. 
  endproperty 
  
  my_ripple_tol_chk: assert(ripple_tol_chk) else `uvm_error(...) 

endinterface : signal_chk_intf

I’d like to expand some other forms of “tolerance checks” and I’d rather not have to rewrite the code over and over, so I’d really prefer to do soemthing like

property tol_chk(local input real signal, exp, tol, local input bit disable_chk);
  @(clk);
  abs(signal-exp) <= tol;   
endproperty

my_dc_tol_chk : assert property(
tol_chk(average,expected_dc_val,dc_tol,disable_dc_chk)) 
`else uvm_error(...) 

my_riiple_tol_chk : assert property(
tol_chk(signal_q.max-signal_q.min,0,ripple_tol,disable_ripple_chk)) 
`else uvm_error(...)

however, I’m getting an error that the real arguments don’thave the right datatype. so I don’t think I can do this directly. Is there a work around to allow me to do this?

2

In reply to paulmiller2010:
abs is a function, thus it should be called from a sequence_match_item
Do this:

 
property tol_chk(local input real signal, exp, tol, local input bit disable_chk);
  real v;
  @(clk);
  (1, v=abs(signal-exp)) ##0 v<= tol;   
endproperty
3

In reply to ben@SystemVerilog.us:

Ben,

thanks for the fast response. However, I am getting an error in the property declaration line. I am getting the error the 3 “real” datatype arguments have the incorrect data type (below for exact language).

property tol_chk( local input real test1, test2, bit disable_chk)
		disable iff(disable_chk) test1 >test2 else `uvm_error("1","test")
	endproperty

xmvlog: *E,SVAFTN (): Formal argument does not have an allowed datatype [16.8.1 (IEEE 1800-2009)].
thanks again,
Paul

4

In reply to paulmiller2010:

There’s no need to declare types on sequence/property’s unless the the is a requirement for it to work.

Also, real numbers in assertion expressions in not legal in SystemVerilog. Some tools have certain enhancements to accept them. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.