SystemVerilog property with a real datatype input argument

SystemVerilog
2

In reply to paulmiller2010:
abs is a function, thus it should be called from a sequence_match_item
Do this:

 
property tol_chk(local input real signal, exp, tol, local input bit disable_chk);
  real v;
  @(clk);
  (1, v=abs(signal-exp)) ##0 v<= tol;   
endproperty