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Evolving Trends in Functional Verification
Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster
2012 Wilson Research Group Functional Verification Study Results
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What to Expect After Adopting the Metrics
Session - Jun 01, 2012 by Andreas Meyer
This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
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Metrics in SoC Verification
Track - Jun 01, 2012 by Andreas Meyer
In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
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Analog Mixed-Signal Verification
Topic - Jun 01, 2012 by None
Today’s ICs increasingly rely on complex mixed-signal functionality with stringent performance and low power requirements for applications in segments including IoT, Automotive, Communications, and Industrials. Verification of these complex mixed-signal ICs is challenging due to the need to ensure that they meet demanding specifications with correct connectivity, functionality, and adequate system performance across analog/digital (A/D) interfaces on the chip. To address these challenges, verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the sub-system level. These mixed-signal simulation solutions need to be fast, accurate, easy to use, and seamlessly integrate into existing analog and digital verification flows.
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Introduction to UVM Connect
Session - May 31, 2012 by Adam Erickson
This session introduces UVM Connect and explains the benefits of adoption. It also reviews the principles and concepts behind the TLM1 and TLM2 standards and reviews the basic connection syntax and semantics of both SystemVerilog and SystemC.
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Introduction to UVM Connect
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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Connections
Session - May 31, 2012 by Adam Erickson
This session shows how to establish TLM-based connections between components in SystemVerilog and SystemC.
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Converters
Session - May 31, 2012 by Adam Erickson
This session shows how to write the converters that are needed to transfer transaction data across the language boundary.
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Converters
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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UVM Command API
Session - May 31, 2012 by Adam Erickson
This session shows how to access and control key aspects of UVM simulation from SystemC.
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UVM Command API
Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
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UVM Connect User Guide
Resource (Reference Documentation) - May 31, 2012 by Adam Erickson
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UVM 1.1b Class Reference
Resource (Reference Documentation) - May 21, 2012 by
v1.1b The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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UVM Connect 2.1.4 Kit
Resource (Tarball) - Feb 20, 2012 by John Stickley
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Verification Horizons - Volume 8, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2012 by Tom Fitzpatrick
"Our kitchen renovation is nearly complete... Just as with verification, the key is to have a plan... take as many contingencies into account as you can... and... be able to handle constrained random stimulus.”
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UVM 1.1a Class Reference
Resource (Reference Documentation) - Dec 01, 2011 by
v1.1a The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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Verification Horizons - Volume 7, Issue 3
Resource (Verification Horizons Archive) - Nov 01, 2011 by Tom Fitzpatrick
"I find myself thinking of how this (kitchen upgrade) relates to upgrading a verification methodology because I’m sure that, by now, you know that that’s how my mind works.”
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Testbench Co-Emulation: SystemC & TLM-2.0
Track - Oct 27, 2011 by John Stickley
This track advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.
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Introduction to SystemC & TLM-2.0
Session - Oct 27, 2011 by John Stickley
In this session, we provide an introduction of virtual prototyping and why co-emulation is so attractive for SoC verification.
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SystemC & TLM-2.0 Testbench Modeling
Session - Oct 27, 2011 by John Stickley
In this session, we will talk about the advantages of using SystemC and OSCI TLM-2.0 standard for testbench modeling. The high level of abstraction of SystemC in conjunction with TLM-2.0 makes it perfect for virtual prototyping with co-emulation. A case study will be used to illustrate the process of implementing an accelerated verification environment.
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The SCE-MI 2.0 Standard
Session - Oct 27, 2011 by John Stickley
In this session, we will talk about the SCE-MI 2.0 standard in the context of how it can be used with emulation. In particular this session describes how SCE-MI is very compatible subset of SystemVerilog 1800 DPI standard, and why it is so relevant for co-emulation.
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The OSCI TLM-2.0 Standard
Session - Oct 27, 2011 by John Stickley
In this session, we will talk about the OSCI SystemC TLM-2.0 standard specifically in the context of how it can be used with emulation. Key areas include loosely-timed modeling, transport interfaces that are capable of transporting transactions and reusable transactions called generic payload.
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Modeling SystemC TLM-2.0 Drivers
Session - Oct 27, 2011 by John Stickley
In this session, we will talk in detail about how to model TLM-2.0 compliant drivers and acceleratable transactors. A case study will be used to show how to implement transactors for a Wishbone Bus protocol.
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SystemC & TLM-2.0 Monitors and Talkers
Session - Oct 27, 2011 by John Stickley
In this session, we will talk in detail about how to model TLM-2.0 compliant transactors. In this particular, we discuss the architecture of passive bus monitors and their associated acceleratable transactors. The Wishbone Bus protocol will be used to show how to implement monitor transactors.