FPGA Verification Capabilities

This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

FPGA Verification

Ray Salemi

Last Updated Aug 2012

Sessions
- Introduction from Harry Foster
  
  This session is an introduction to various code coverage metrics and how to apply them.
  Track Aug 30, 2012 by Harry Foster
  
  FPGA Verification
- Overview and Welcome
  
  This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Code Coverage
  
  This session is an introduction to various code coverage metrics and how to apply them.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Test Planning
  
  This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Applied Assertions
  
  This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Transactions
  
  This session shows you how to create a transaction level test bench using modules instead of object.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Self-Checking Testbenches
  
  This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Automatic Stimulus
  
  This session introduces constrained-random stimulus for automatic stimulus generation.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
- Functional Coverage
  
  This session shows you how to implement functional coverage using SystemVerilog covergroups.
  Track Aug 30, 2012 by Ray Salemi
  
  FPGA Verification
Overview

Today we are witnessing a phenomenal increase in FPGA design starts as one means to reduce risk. In fact, Gartner recently reported that FPGAs now have a 30-to-1 edge over ASICs in design starts. Although FPGAs have traditionally been relegated to glue logic, low-volume production, or prototype parts used for analysis, this is no longer the case. Gate count and advanced features found in today’s FPGAs have increased dramatically to compete with capabilities traditionally offered by ASICs alone.
The change in FPGA capabilities has results in the emergence of advanced FPGA system-on-chip (SoC) solutions, which includes the integration of third-party IP, DSPs, and multiple microprocessors—all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address. This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.