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Block Level Functional Coverage Example
Chapter - Dec 04, 2013 by Harry Foster
Block level functional verification can take full advantage of the he fact that all the block interfaces are exposed and can be stimulated seperately with complete freedom. The desired outcome of the verification process is that the block has been thoroughly tested so that it can reused at a higher-level of integration with complete confidence.
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Test Plan to Functional Coverage
Chapter - Dec 04, 2013 by Harry Foster
Arriving at functional coverage closure is a process that starts with the functional specification for the design, which is analyzed to determine: What features need to be tested Under what conditions the features need to be tested What testbench infrastructure is required to drive and monitor the design's interfaces How the testbench will check that the features work
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Bus Protocol Coverage
Chapter - Dec 04, 2013 by Harry Foster
A bus protocol defines how data is transferred between master and slave devices on the bus. The protocol specifies which signals are used to qualify when the master is making a request and when the slave is ready to respond to that request.
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UART Example Covergroups
Chapter - Dec 04, 2013 by Harry Foster
The covergroup examples on this page are implementations of the functional coverage descriptions on the Block Level Functional Coverage Example page. They illustrate different aspects of how-to code covergroups and are described here to allow you to see how the high-level functional descriptions map to concrete implementations. They are presented in the same order as they are described on the higher-level page.
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Requirements Writing Guidelines
Chapter - Dec 04, 2013 by Harry Foster
When creating a test plan , requirements to have a successful chip need to be recorded in a useful, easy to digest manner. The following rules and guidelines will help to ensure this happens. It is a good idea for the verification team to compile a list such as this before starting the planning process and to divide them up into rules (must be followed) and suggestions (good ideas).
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Sequencer Arbitration (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Example showing the differences between the different sequencer arbitration algorithms.
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Functional Coverage Metrics
Chapter - Dec 04, 2013 by Harry Foster
The objective of functional verification is to determine if the design requirements, as defined in our specification, are functioning as intended. But how do you know if all the specified functionality was actually implemented?
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Datapath Example
Chapter - Dec 04, 2013 by Harry Foster
A datapath block takes an input data stream and implements a transform function that generates the output data. The transfer function may have settings which change its characteristics, or it may be a fixed implementation. In its path from the input to the output, the data does not interact with other blocks, hence the term datapath. Examples of datapath blocks include custom DSP functions, modems, encoders and decoders and error correction hardware.
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BiQuad IIR Filter Test Plan
Chapter - Dec 04, 2013 by Harry Foster
As part of the verification planning process a functional coverage/test plan should be created. In the case of the BiQuad IIR filter, the primary concern is to check that it can be configured to act as a low, high and band pass filter in the audio frequency range and that it functions correctly in each of these modes.
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Kinds of Coverage
Chapter - Dec 04, 2013 by Harry Foster
No single metric is sufficient at completely characterizing the verification process. For example, we might achieve 100% code coverage during our simulation regressions. However, this would not mean that 100% of the functionality was verified.
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BiQuad IIR Filter Example Covergroups
Chapter - Dec 04, 2013 by Harry Foster
The functional coverage model for the BiQuad IIR filter is based on ensuring that all variations of 3 sets of variables have been checked by the stimulus: The filter type - Low Pass, High Pass and Band Pass The filter specification, in terms of the coefficients - b10, b11, b12, a10, a11 The input frequency, measured in hertz To create the coverage model, we need to create a set of covergroups and a coverage monitor.
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Wishbone SoC Test Plan
Resource (Reference Documentation) - Dec 04, 2013 by Verification Methodology Team
Wishbone SoC test plan spreadsheet example (.xml)
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WB Mac Analysis (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Compressed code archive file.
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Code Coverage Metrics
Chapter - Dec 04, 2013 by Harry Foster
In this section, we introduce various coverage metrics associated with a design model's implicit implementation coverage space. In general, these metrics are referred to as code coverage or structural coverage metrics.
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APB3 Protocol Test Plan
Chapter - Dec 04, 2013 by Harry Foster
During the verification planning process, a test plan should be created that lists the features of a design, how they are to be verified and how test closure will be achieved. The APB3 protocol monitor is a reusable verification component (VIP) and it can be reused when verifying any design which has an APB3 bus interface.
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BiQuad Example (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
In this class of design, the stimulus pumps data through the design datapath and compares the output against a reference model. The functional coverage is primarily about ensuring that the algorithm 'knobs' have been tested sufficiently.
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Sequencer Grab Lock (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Illustrates the use of lock and grab by a sequence to gain exclusive access to a sequencer for its sequence_items.
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Coverage
Cookbook - Dec 04, 2013 by Harry Foster
The Coverage Cookbook describes the different types of coverage that are available to keep track of the progress of the verification process, how to create a functional coverage model from a specification and provides examples of how to implement functional coverage for different types of designs.
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Coverage Cookbook
Resource (Cookbook) - Dec 04, 2013 by Harry Foster
The Coverage Cookbook describes the different types of coverage that are available to keep track of the progress of the verification process, how to create a functional coverage model from a specification and provides examples of how to implement functional coverage for different types of designs.
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Interrupts - Simple (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Simple, single level interrupt service routine example.
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Slave Agent with Multiple Sequence Items (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Example showing how to implement a reactive slave agent with phase specific sequence items.
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Slave Agent (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Example showing how to implement a reactive slave agent.
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Parameterized Virtual Interface (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Illustrates how to handle a parameterized virtual interface using the uvm_config_db.
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UVM Block Level Testbench (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Example of a block level UVM testbench.
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Sub-system Level Testbench (.tgz)
Resource (Tarball) - Dec 04, 2013 by VM Team
Example of a sub-system UVM testbench reusing block level components.