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2419 Results
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Questa Connectivity Check: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo assertions and results and a quick debug showing the QFL waveforms using Questa Connectivity Check.
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CoverCheck: Accelerating Coverage Closure
Session - Jun 05, 2015 Mark Eslinger
In this session, we'll demonstrate how automated formal techniques can be used to keep the project moving forward by exhaustively determining the reachability or unreachability of coverage elements, grant persistent waivers to areas that can be safely excluded, and how the master coverage database can be automatically updated with the current coverage score.
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Formal Assertion-Based Verification
Track - Jun 05, 2015 Mark Eslinger
In this track, you will learn how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines.
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Questa CoverCheck: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo the Questa CoverCheck tool and will review features including the details window, coverage checks window, and source debug features.
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Register Check: Memory Mapped Register Verification
Session - Jun 05, 2015 Mark Eslinger
In this session, we’ll take a quick overview of memory mapped verification and some of the challenges users face with verifying these design constructs. We’ll look at how Questa Register Check can improve speed and completeness in your memory mapped register verification flows.
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Introduction to Formal Assertion-Based Verification
Session - Jun 05, 2015 Joe Hupcey
In this session, we will learn about various formal verification techniques; what they are, how to utilize them, and benefits received from advanced formal technologies.
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Formal Assertion-Based Verification Introduction & Overview
Resource (Slides (.PDF)) - Jun 05, 2015 Joe Hupcey
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Questa Register Check: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo memory mapped register checkers generated results that can be debugged in the using Questa Register Check.
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Formal Model Checking
Session - Jun 05, 2015 Mark Eslinger
In this session, we'll share some basic tips for getting started with direct property checking, how to setup the analysis for rapidly reaching a solution, and how to answer the question, “Do I have enough assertions?"
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Basic Formal Closure: Black Boxing and Cutpoint
Resource (Slides (.PDF)) - Jun 05, 2015 Mark Eslinger
This session will show two simple techniques to safely limit the states the engines need to process, enabling more in-depth results.
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Basic Formal Closure: Black Boxing and Cutpoint
Session - Jun 05, 2015 Mark Eslinger
At some point formal engines will begin to struggle under the weight of the state space. This session will show two simple techniques to safely limit the states the engines need to process, enabling more in-depth results.
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Formal Model Checking
Resource (Slides (.PDF)) - Jun 05, 2015 Mark Eslinger
In this session, we'll share some basic tips for getting started with direct property checking.
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Questa PropCheck: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo the Questa PropCheck tool and will review features including the details window, properties window, along with source, waveform and schematic debug features.
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SecureCheck: How Secure is your Design?
Session - Jun 05, 2015 Mark Eslinger
In this session, we'll show how to exhaustively prove the integrity of the hardware root of trust with your RTL and a clear text, human and machine-readable spreadsheet to specify the critical storage and allowed access paths.
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Questa SecureCheck: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo the Questa SecureCheck tool and will review features including the details window, properties tab, waveform and schematic views.
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X-Check: Mitigating X Effects in your Verification
Session - Jun 05, 2015 Mark Eslinger
In this session, we’ll take a quick look at the various types of X effects and how they can impact your design. We’ll also look at some common sources of X which are the originators of these effects.
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Questa X-Check: Demo
Demo - Jun 05, 2015 Mark Eslinger
This session will demo finding X-corruption in your design using Questa X-Check.
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Part 6: FPGA Verification Language and Library Adoption Trends
Resource (Verification Horizons Blog) - Jun 03, 2015 Harry Foster
This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on FPGA verification techniques and technologies adoption trends, as identified by the 2014 Wilson Research Group study. In this blog, I’ll present FPGA design and verification language trends, as identified by the Wilson Research Group study.
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UVM Debug? Beyond Logfiles
Conference - Jun 01, 2015 Rich Edelman
Today UVM testbenches are widely used to generate stimulus variants, and collect functional coverage, and today's UVM testbenches are complex object-oriented software programs in their own right. And yet, debugging these testbenches is sometimes relegated to manually printing large quantities of information to the transcript file and trawling through it for snippets and symptoms. In this session, you will learn about tips and tricks to move beyond logfiles, towards better UVM Debug.
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UVM Debug? Beyond Logfiles
Resource (Slides (.PDF)) - Jun 01, 2015 Rich Edelman
In this session you will learn about tips and tricks to move beyond logfiles, towards better UVM Debug.
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New School Coverage Closure
Webinar - May 29, 2015 Mark Eslinger
In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.
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UVMC 2.3.1 Library
Resource (Reference Documentation) - May 15, 2015 John Stickley
The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
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Technical Paper - SVA Local Variable Coding Guidelines for Efficient Use
Resource - May 15, 2015
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Questa Simulation: Power Aware
Demo - May 12, 2015 Chuck Seeley
In this demo, you will learn the UPF based Power Aware features available in Questa PASim.
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Part 5: FPGA Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - May 11, 2015 Harry Foster
This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on the effectiveness of verification in terms of FPGA project schedule and bug escapes. In this blog, I present verification techniques and technologies adoption trends, as identified by the 2014 Wilson Research Group study.