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Part 1: FPGA Design Trends

Resource (Verification Horizons Blog) - Aug 15, 2016 Harry Foster

In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. Let’s begin by examining embedded processor trends targeted at a general FPGA implementation. Our 2016 study found that 59% of all FPGA designs contained one or more embedded processors, as shown in Fig. 1-1. This is a slight increase over our 2014 study. Most of this growth is in the number of FPGA projects creating designs containing more than one embedded processor.
Staying Competitive with FPGA Advanced Verification

Webinar - Aug 10, 2016 Bryan Ramirez

In this session you will learn about trends in the FPGA industry that are pushing the need for advanced verification.
Prologue: The 2016 Wilson Research Group Functional Verification Study

Resource (Verification Horizons Blog) - Aug 08, 2016 Harry Foster

This is the first in a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group Functional Verification Study blogs ( click here ), I plan to begin this set of blogs with an exclusive focus on FPGA trends.
Understanding and Minimizing Study Bias (2016 Study)

Resource (Verification Horizons Blog) - Aug 08, 2016 Harry Foster

This blog is a continuation of a series of blogs that present the highlights from the 2016 Wilson Research Group Functional Verification Study (for a background on the study, click here ). This blog, which discusses the issue of study bias and what we did to address these concerns, is basically a repeat of this topic from my 2014 blog series. However, there are a few observations related specifically to our 2016 study worth mentioning.
Matlab UVM Example (.tgz)

Resource (Tarball) - Jun 24, 2016 VM Team

Compressed code archive file.
Trends in Functional Verification

Resource (Slides (.PDF)) - Jun 20, 2016 Harry Foster
Debug Data API Update

Resource (Slides (.PDF)) - Jun 20, 2016 Rich Edelman
Verifying Safety-Related Systems

Resource (Slides (.PDF)) - Jun 20, 2016 Dr. Mike Bartley

The traditional environments for safety-related hardware and software such as avionics, rail and nuclear have been joined by others (such as automotive and medical devices) as systems become increasingly complex and ever more reliant on embedded software.
Get Ready for Portable Stimulus

Resource (Slides (.PDF)) - Jun 20, 2016 Tom Fitzpatrick

This session will clearly explain what Portable Stimulus is (and what it isn't), how the Portable Stimulus Working Group is tackling the problem, and what the solution is likely to be.
Various Methods for Debugging Software in Emulation

Resource (Slides (.PDF)) - Jun 20, 2016 Russell Klein
DAC 2016 Academy PDF Presentation: UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

Resource - Jun 20, 2016
Verification IP and Memory Models Improve Productivity and Reduce Risk

Resource (Slides (.PDF)) - Jun 20, 2016 Mark Olen
DAC 2016 Academy PDF Presentation: SystemVerilog Assertions - Bind files & Best Known Practices - Sunburst Design

Resource - Jun 20, 2016
Back to the Stone Ages for Advanced Verification

Resource (Slides (.PDF)) - Jun 20, 2016 Neil Johnson
DAC 2016 Academy PDF Presentation: Get a Head Start on the New UVM Standard

Resource - Jun 20, 2016
SW-HW Pipe

Resource (Pattern) - Jun 10, 2016 Harry Foster

The SW-HW Pipe Pattern is an implementation pattern that provides a buffered one-way communication channel between separated HVL and HDL module hierarchies in a dual-domain partitioned testbench. Writing to and reading from the pipe can be done at any rate. Writes block if the pipe is full. Data written to an empty pipe is available for reading on the next clock cycle. Reading from an empty pipe has a well-defined behavior.
How Formal Techniques Can Keep Hackers from Driving You into a Ditch

Article - Jun 01, 2016 Joe Hupcey

In this article we will show how a mathematical, formal analysis technique can be applied to ensure that this secure storage cannot (A) be read by an unauthorized party or accidentally “leak” to the outputs or (B) be altered, overwritten, or erased by unauthorized entities. We will include a real-world case study from a consumer electronics maker that has successfully used this technology to secure their products from attacks 24/7/365.
Simplifying HDCP Verification Using Questa Verification IP

Article - Jun 01, 2016 Raman Jain, Priya Minocha - Siemens EDA

This article describes various challenges in the field of verifying and debugging HDCP protected interfaces (HDMI and DisplayPort), and how Mentor’s QVIP makes this task easier for users by providing simple to use APIs and debug messages.
No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model

Article - Jun 01, 2016 Rich Edelman

SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
Accelerating Networking Products to Market

Article - Jun 01, 2016 Dr. Lauro Rizzatti - Rizzatti LLC

Take a step down the stack beyond optical networks, switches, routers and software-defined networking to consider the networking system on chip (SoC), the brains of the network infrastructure.
Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow

Article - Jun 01, 2016 Francis Raguin - Barco N.V.

RTCA DO-254 - Guidance document for the development of hardware components for airborne equipment – requires the functional behavior of FPGAs to be silicon proven on the final application hardware:
Extending UVM Verification Models for the Analysis of Fault Injection Simulations

Article - Jun 01, 2016 Dan Alexandrescu, Adrian Evans - IROC Technologies

In this article, we show how the components of a UVM functional verification environment can easily be extended to record additional information about the types of errors that have occurred. This additional information can be used to classify failing tests based on their system level impact (e.g. Silent Data Corruption, Detected Uncorrected Error, etc.). We present an architecture that can be implemented on the Questa Verification Platform for designs with UVM DVE.
Saving Time and Improving Quality with a Specification to Realization Flow

Article - Jun 01, 2016 Kiran Sharma, Bhavna Agarwal - Agnisys Technology Pvt. Ltd.

This article describes our efforts to reap a higher level of productivity and quality by combining these two complementary tools. We use the ISequenceSpec tool suite for describing the low-level sequences for the register memories in the addressable region of the design. These are then transformed into UVM sequences, firmware and sequences for other target domains.
Solve UVM Debug Problems with the UVM Vault

Article - Jun 01, 2016 Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks

Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices.
Parameterized UVM Tests

Resource (Pattern) - May 02, 2016 Harry Foster

Parameters used in a design in most cases must also be used in a testbench to ensure proper connections and communication can be performed. Parameterized UVM tests (which are not available by default) provide an easy mechanism for sharing of parameters.