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Technical Paper - SVA Local Variable Coding Guidelines for Efficient Use

Resource - May 15, 2015 by
Questa Simulation - Power Aware

Demo - May 12, 2015 by Chuck Seeley

In this demo, you will learn the UPF based Power Aware features available in Questa PASim.
FPGA Trends in Functional Verification - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the FPGA verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
ASIC/IC Trends in Functional Verification - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the IC/ASIC verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Slides (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Paper (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Webinar - Mar 31, 2015 by Tom Fitzpatrick

This session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly and become productive with using UVM for the verification of most types and sizes of digital designs modeled in VHDL, Verilog or SystemVerilog. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.
UVMC 2.3.0 Library

Resource (Reference Documentation) - Mar 15, 2015 by

v2.3.0 The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Does Design Size Influence First Silicon Success?

Article - Mar 11, 2015 by Harry Foster

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification at that point in time. However, after the 2004 study, no additional Collett studies were conducted, which left a void in identifying industry trends.
Successive Refinement: A Methodology for Incremental Specification of Power Intent

Article - Mar 11, 2015 by Adnan Khan, John Biggs & Eamonn Quigley - Arm

In this article, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system. We explain how a system’s power management architecture can be specified in a technology-independent manner and verified abstractly, before implementation. We also explain how implementation information can be added later.
Power Aware RTL Verification of USB 3.0 IPs

Article - Mar 11, 2015 by Gayathri SN, Badrinath Ramachandra - L&T Technology Services Limited

This article describes a specific Power Management scheme used in a USB 3.0 Device IP controller. It also describes how Questa Power Aware helped IP designers realize reliable, accurate and scalable low power architectures and comprehensive verification of these architectures. Additionally, this also shares the experience in using the UPF to define various power domains, isolation strategies and methods to control power states from the testbench.
Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 by Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Small, Maintainable Tests

Article - Mar 11, 2015 by Ashley Winn - Sondrel IC Design Services

In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested.
Functional Coverage Development Tips: Do’s and Don'ts

Article - Mar 11, 2015 by Samrat Patel, Vipul Patel - eInfochips

The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort.
UVM Connect 2.3.0 Kit

Resource (Tarball) - Mar 10, 2015 by John Stickley
UVM Connect 2.3.0 Primer

Resource (Reference Documentation) - Mar 10, 2015 by John Stickley
Coverage Data Exchange Is No Robbery…Or Is It?

Resource (Paper (.PDF)) - Mar 03, 2015 by Darron May

Coverage is extremely important to the modern verification flow. Most vendors have already figured that unifying data across all verification engines leads to a more efficient and integrated environment. There are many challenges to be solved unifying and sharing data across a single vendor’s tool set which are further complicated when wanting to share data across multiple vendors’ tool sets.
Coverage Data Exchange Is No Robbery…Or Is It?

Resource (Poster Paper) - Mar 03, 2015 by Darron May

In this poster paper, presented at DVCon 2015, you learn more that the Unified Coverage Database was architected in 2005 to unify coverage collection across all verification engines, UCDB was first released within Questa and ModelSim in early 2006 as a way of natively storing, analyzing and reporting on functional coverage, code coverage and assertions.
Coverage Data Exchange Is No Robbery…Or Is It?

Paper - Mar 03, 2015 by Darron May

Over the last few years all the major vendors have realized that unifying the way coverage is stored in a common database allows the results of multiple verification tools to be combined and for these tools to share the data to improve coverage closure. Simulation, Emulation and Formal engines should all be using the same database to provide the user with the complete picture, and allow the analysis of all data in a common way.
UVM Connect 2.3 Kit

Resource (Tarball) - Feb 18, 2015 by John Stickley
Coverage Cookbook - Japanese Release

Resource (Cookbook Japanese Translation) - Jan 14, 2015 by
Introduction to Questa X-Check

Webinar - Dec 20, 2014 by Doug Smith

In this session, you will learn how Questa X-Check finds sources of X in your design and identifies issues where X is propagated and corrupts properly initialized registers.
Power Aware Verification in Mixed-Signal Simulation

Resource (Paper (.PDF)) - Dec 10, 2014 by

Power efficiency is a very important metric in designing mobile and other industrial SoCs. Various power saving techniques are used to reduce power consumption. To verify the power distribution network and power state transitions in SoC designs, power-aware verification is performed with the power architecture described in UPF. Many of those SoCs are mixed-signal in nature and have power-regulation functionality on the chip.
Introduction to Questa CDC

Webinar - Nov 12, 2014 by Doug Smith

In this session, you will learn how the Questa Clock-Domain Crossing (CDC) solution focuses on the interaction between these clock-domains.