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2413 Results
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An Emulation Strategy for AI and ML Designs
Resource (Slides (.PDF)) - Jul 15, 2019 Vijay Chobisa
The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session.
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Tessent: DFT Enablement for AI Devices
Conference - Jul 15, 2019 Geir Eide
Artificial Intelligence (AI) and other leading-edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. In this session, we'll investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
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Tessent: DFT Enablement for AI Devices
Resource (Slides (.PDF)) - Jul 15, 2019 Geir Eide
In this session, we'll learn about some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed
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Deep Learning Accelerator Using HLS
Resource (Slides (.PDF)) - Jul 15, 2019
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Streamlining Plan & Requirements Driven Verification
Resource - Jul 12, 2019
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Improving Verification Throughput of Today’s Complex Mixed-Signal ICs
Resource (Slides (.PDF)) - Jul 12, 2019
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Selecting the Most Productive SoC Design Verification Techniques
Resource (Slides (.PDF)) - Jul 12, 2019
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Veloce HYCON - OS-aware IP Development Solution
Resource (Slides (.PDF)) - Jul 12, 2019
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RISC-V Core and SoC: Compliance, Verification, Customization
Resource (Slides (.PDF)) - Jul 11, 2019 Larry Lapides
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Emulation to Prototype - What’s Eating Your Productivity?
Resource (Slides (.PDF)) - Jul 11, 2019
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Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity
Resource (Slides (.PDF)) - Jul 11, 2019 Tom Fitzpatrick
In this session, you will learn how you to use Portable Stimulus to leverage the built-in infrastructure in QVIP and your UVM environment to realize truly coverage-driven scenario-level functional coverage to keep you ahead of the productivity curve.
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Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification
Webinar - Jul 10, 2019 Kurt Takara
This session explains the importance of a complete Clock-Domain Crossing (CDC) methodology to produce error-free silicon.
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Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification
Resource (Slides (.PDF)) - Jul 10, 2019 Kurt Takara
This session explains the importance of a complete CDC methodology to produce error-free silicon.
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Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps
Paper - Jul 07, 2019 Madhur Bhargava - Siemens EDA
The effective verification of low power designs has been a challenge for many years now. The IEEE 1801 standard for modeling low power objects and concepts is continuously evolving to address the low power challenges of today’s complex designs. One of the traditional yet effective way to verify the design is to write SystemVerilog (SV) assertions to ensure that right design behavior is met.
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Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps
Resource (Paper (.PDF)) - Jul 07, 2019 Madhur Bhargava - Siemens EDA
The low power designs today are incredibly complex with intricate power architecture. A thorough low-power verification is must for such designs as any power bug left can cause huge setback. In this paper we discuss the challenges with the current low-power design checking and how a proposed method can be addressed with the help of UPF 3.0.
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Transaction Recording & Debug with Questa & Visualizer
Webinar - Jun 20, 2019 Rich Edelman
This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.
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Integrated Approach to Power Domain/Clock-Domain Crossing Checks
Webinar - Jun 20, 2019 Ashish Amonkar
Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
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Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
Resource (Paper (.PDF)) - Jun 15, 2019 Thomas Ellis
In this paper, you will learn that covergroups are an incredibly powerful component of verification, however, they can be a bit difficult to set up properly. By following recommendations, outlined in this paper, armed with a better understanding of the effect covergroup options have on the results of verification, you can be sure to get the most out of your verification.
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Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify Use Models
Paper - Jun 15, 2019 Thomas Ellis
Covergroups are an incredibly powerful component of verification, however they can be difficult to set up properly. This paper outlines a set of guidelines for writing an unambiguous functional coverage model. It shows how potential pitfalls, such as covergroups that cannot be merged, unnecessary performance overhead, or restricted debug visibility, can be avoided.
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A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
Resource (Paper (.PDF)) - Jun 11, 2019 Kurt Takara
Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs. This methodology is a 3-step process that provides a requirements-based approach for RDC design and verification.
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A Specification-Driven Methodology for the Design and Verification of RDC Logic
Paper - Jun 11, 2019 Kurt Takara
With the increasing complexity of today's System-on-a-Chip (SoC) designs, reset architectures have also increased in complexity. Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset-domain crossing (RDC) paths in large SoC designs.
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Reusable UPF - Transitioning from RTL to Gate Level Verification
Resource (Paper (.PDF)) - Jun 11, 2019
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What's Missing and What Should Be Next for SystemVerilog
Resource (Slides (.PDF)) - Jun 03, 2019 Cliff Cummings
Cliff Cummings shares possible new features that would help engineers create more concise designs while making fewer mistakes. The proposed features would also increase customer satisfaction with EDA tools and require fewer queries and complaints to EDA vendors.
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Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer
Resource (Slides (.PDF)) - Jun 03, 2019 Sumit Vishwakarma
In this session we will dive into a simple scenario and demonstrate how you can take advantage of Symphony and the Visualizer Debug Environment to debug RNM boundary scenarios in case of a functional failure.
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Debugging Your Design in a Heterogeneous Environment
Resource (Slides (.PDF)) - Jun 03, 2019 Rich Edelman
In this session we will address debug needs of today's complex environment using Questa Visualizer Debug.