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Predictable and Scalable End-to-End Formal Verification

Article - Mar 03, 2021 Dr. Ashish Darbari

In this article, we discuss why formal verification adoption has been limited in industry, and how abstraction-based methodology in formal verification can help DV engineers become successful in adopting formal property checking more widely. Abstraction is the key to obtaining scalability and predictability. It provides an efficient bug-hunting technique and helps in establishing exhaustive proof convergence.
Enabling RISC-V Based System Development

Article - Mar 03, 2021 Sandeep Nasam, Sagar Thakran - Logic Fruit Technologies

This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.
The Six Steps Of RISC-V Processor Verification Including Vector Extensions

Article - Mar 03, 2021 Larry Lapides

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.
Trends in Functional Verification

Webinar - Mar 02, 2021 Harry Foster

Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.
I'm Excited About Formal...My Journey From Skeptic to Believer

Webinar - Feb 26, 2021 Neil Johnson

In this session, you will learn the about unlikely journey into formal for a verification engineer who’s spent an entire career using simulation.
A Methodology for Comprehensive CDC Analysis

Webinar - Feb 26, 2021 Atul Sharma

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
A Methodology for Comprehensive CDC Analysis

Resource (Slides (.PDF)) - Feb 26, 2021 Atul Sharma

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
Epilogue: 2020 Study Summary and Key Findings

Resource (Verification Horizons Blog) - Feb 18, 2021 Harry Foster

This is the last in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
The ABC of Formal Verification

Webinar - Feb 11, 2021 Dr. Ashish Darbari

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.
Conclusion: Deeper Dive into Non-Trivial Bug Escapes

Resource (Verification Horizons Blog) - Feb 10, 2021 Harry Foster

Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes. This maturity is likely due to the growing complexity of designs and related efforts to control cost and engineering headcount through the adoption of FPGA design and verification solutions that increase productivity.
Verification Learns a New Language

Resource (Verification Horizons Blog) - Feb 08, 2021 Ray Salemi

Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
I Didn't Know Visualizer Could Do that

Resource (Slides (.PDF)) - Feb 05, 2021 Rich Edelman
Part 12: IC/ASIC Verification Results Trends

Resource (Verification Horizons Blog) - Feb 03, 2021 Harry Foster

In this blog, I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs. A metric often tracks to measure efficiency is ASIC/IC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 68 percent of IC/ASIC projects were behind schedule.
ISO 26262 Creating an Optimal Safety Architecture

Resource (Slides (.PDF)) - Feb 02, 2021 Jacob Wiltgen
ISO 26262: Creating an Optimal Safety Architecture

Session - Feb 02, 2021 Jake Wiltgen

In this session, you will gain an understanding of the core challenges defining an optimal safety architecture. This session will describe the pros and cons of various safety features deployed within a larger safety architecture. Additionally, a workflow and methodology will be described which guides the creation and also validates the safety architecture prior to executing an expensive fault campaign.
Part 11: IC/ASIC Power Management Trends

Resource (Verification Horizons Blog) - Jan 27, 2021 Harry Foster

In this blog, I focus on low power trends. In figure 11-1, we see that the percentage of design projects who actively manage power by design size. The data suggest that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.
Mil/Aero Analysis Functional Verification Study - 2020

Resource (Paper (.PDF)) - Jan 20, 2021 Harry Foster
Part 9: ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Jan 14, 2021 Harry Foster

In this blog I examine IC/ASIC project verification technology adoption trends. The IC/ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of IC/ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2020 as shown in Figure 9-1.
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Jan 06, 2021 Harry Foster

In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity. Figure 8-1 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product.
MathWorks® Integration

Resource (Slides (.PDF)) - Dec 29, 2020 Bob Oden

In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.
MathWorks® Integration

Session - Dec 29, 2020 Bob Oden

In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Dec 22, 2020 Harry Foster

In this blog, I present trends related to various aspects of design to illustrate growing design complexity. One interesting observation from this year’s study is the continue increase in design projects working on designs less than 1M gates. This is due to a number of projects working on smaller sensor chips for IoT and automotive devices. This can potentially yield some interesting results in the study.
Part 6: FPGA Verification Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Dec 16, 2020 Harry Foster

In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Dec 09, 2020 Harry Foster

In this blog, I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly.
Embedded Software Debug Using Codelink and Visualizer

Webinar - Dec 08, 2020 Tomasz Piekarz

In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.