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A Methodology for Comprehensive CDC Analysis
Resource (Slides (.PDF)) - Feb 26, 2021 Atul Sharma
In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
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Epilogue: 2020 Study Summary and Key Findings
Resource (Verification Horizons Blog) - Feb 18, 2021 Harry Foster
This is the last in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
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The ABC of Formal Verification
Webinar - Feb 11, 2021 Dr. Ashish Darbari
This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.
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Conclusion: Deeper Dive into Non-Trivial Bug Escapes
Resource (Verification Horizons Blog) - Feb 10, 2021 Harry Foster
Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes. This maturity is likely due to the growing complexity of designs and related efforts to control cost and engineering headcount through the adoption of FPGA design and verification solutions that increase productivity.
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Verification Learns a New Language
Resource (Verification Horizons Blog) - Feb 08, 2021 Ray Salemi
Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
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I Didn't Know Visualizer Could Do that
Resource (Slides (.PDF)) - Feb 05, 2021 Rich Edelman
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Part 12: IC/ASIC Verification Results Trends
Resource (Verification Horizons Blog) - Feb 03, 2021 Harry Foster
In this blog, I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs. A metric often tracks to measure efficiency is ASIC/IC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 68 percent of IC/ASIC projects were behind schedule.
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ISO 26262 Creating an Optimal Safety Architecture
Resource (Slides (.PDF)) - Feb 02, 2021 Jacob Wiltgen
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ISO 26262: Creating an Optimal Safety Architecture
Session - Feb 02, 2021 Jake Wiltgen
In this session, you will gain an understanding of the core challenges defining an optimal safety architecture. This session will describe the pros and cons of various safety features deployed within a larger safety architecture. Additionally, a workflow and methodology will be described which guides the creation and also validates the safety architecture prior to executing an expensive fault campaign.
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Part 11: IC/ASIC Power Management Trends
Resource (Verification Horizons Blog) - Jan 27, 2021 Harry Foster
In this blog, I focus on low power trends. In figure 11-1, we see that the percentage of design projects who actively manage power by design size. The data suggest that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.
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Mil/Aero Analysis Functional Verification Study - 2020
Resource (Paper (.PDF)) - Jan 20, 2021 Harry Foster
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Part 9: ASIC Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - Jan 14, 2021 Harry Foster
In this blog I examine IC/ASIC project verification technology adoption trends. The IC/ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of IC/ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2020 as shown in Figure 9-1.
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Part 8: IC/ASIC Resource Trends
Resource (Verification Horizons Blog) - Jan 06, 2021 Harry Foster
In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity. Figure 8-1 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product.
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MathWorks® Integration
Resource (Slides (.PDF)) - Dec 29, 2020 Bob Oden
In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.
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MathWorks® Integration
Session - Dec 29, 2020 Bob Oden
In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.
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Part 7: IC/ASIC Design Trends
Resource (Verification Horizons Blog) - Dec 22, 2020 Harry Foster
In this blog, I present trends related to various aspects of design to illustrate growing design complexity. One interesting observation from this year’s study is the continue increase in design projects working on designs less than 1M gates. This is due to a number of projects working on smaller sensor chips for IoT and automotive devices. This can potentially yield some interesting results in the study.
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Part 6: FPGA Verification Language and Library Adoption Trends
Resource (Verification Horizons Blog) - Dec 16, 2020 Harry Foster
In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
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Part 5: FPGA Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - Dec 09, 2020 Harry Foster
In this blog, I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly.
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Embedded Software Debug Using Codelink and Visualizer
Webinar - Dec 08, 2020 Tomasz Piekarz
In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.
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Part 4: FPGA Verification Effort Trends (Continued)
Resource (Verification Horizons Blog) - Dec 02, 2020 Harry Foster
In my previous blog I discussed verification effort trends in terms of project time spent in verification, as well as increasing headcount as indicated by the rising mean peak number of design and verification engineers working on FPGA projects. In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process.
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Visualizer Coverage: Debug and Visualize All Your Coverage
Webinar - Nov 19, 2020 Athira Panicker
In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.
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Part 3: FPGA Verification Effort Trends
Resource (Verification Horizons Blog) - Nov 18, 2020 Harry Foster
In my previous blog, I presented the findings from our new study related to how successful FPGA projects are in terms of verification effectiveness. In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…”
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Part 2: FPGA Verification Effectiveness Trends
Resource (Verification Horizons Blog) - Nov 10, 2020 Harry Foster
In this blog, I present the findings from our new study related how successful FPGA projects are in terms of verification effectiveness. IC/ASIC projects have often used the metric “number of required spins before production” as a benchmark to assess a project’s verification effectiveness. Historically, about 30% of IC/ASIC projects are able to achieve 1st silicon success, and most successful designs are productized on the 2nd silicon spin. Unfortunately, FPGA projects have no equivalent metric.
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I’m Excited About Formal…My Journey From Skeptic to Believer
Resource (Slides (.PDF)) - Nov 09, 2020
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Part 1: FPGA Design Trends
Resource (Verification Horizons Blog) - Nov 05, 2020 Harry Foster
In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021. The FPGA semiconductor market is valued at about $5 billion. The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4%.