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Celebrating 10 Years of the UVM

Article - Mar 03, 2021 by Mark Peryer

Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.
Purging CXL Cache Coherency Dilemmas

Article - Mar 03, 2021 by Nikhil Jain, Gaurav Manocha - Siemens EDA

The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators' usage. The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing.
What is “Verification” in the Context of DO-254 (Avionics) Programs?

Article - Mar 03, 2021 by Michelle Lange, Jeff Reeve and Tammy Reeve - Patmos Engineering Services

If you are a hardware design or verification engineer, you probably have a good idea of what verification entails. However, add compliance to RTCA/DO-254 as a requirement, and suddenly the definition of “verification” may not be so clear. First, the term “verification” must be understood alongside the synergistic term “validation.” Next, in a DO-254 context, verification spans a wider scope than it does traditionally, so understanding this is crucial.
Formal Etiquette for Code Coverage Closure

Article - Mar 03, 2021 by Ajeetha Kumari, Arunachalam R and Satheesh Ethiraj - VerifWorks

Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.
A Formal Verification Technique for Complex Arithmetic Hardware

Article - Mar 03, 2021 by Dr. Sam Elliott - Imagination Technologies

With more emphasis within the electronics industry on high-performance and shorter time to market, the need for high-confidence and high-quality end-to-end verification is becoming more and more important. This is especially true on the heavily optimized arithmetic datapath blocks most used in modern compute and neural network applications. Missed bugs can delay projects and be costly to reputations, and, at the very least, be likely to sap performance.
Predictable and Scalable End-to-End Formal Verification

Article - Mar 03, 2021 by Dr. Ashish Darbari

In this article, we discuss why formal verification adoption has been limited in industry, and how abstraction-based methodology in formal verification can help DV engineers become successful in adopting formal property checking more widely. Abstraction is the key to obtaining scalability and predictability. It provides an efficient bug-hunting technique and helps in establishing exhaustive proof convergence.
Enabling RISC-V Based System Development

Article - Mar 03, 2021 by Sandeep Nasam, Sagar Thakran - Logic Fruit Technologies

This article focuses on providing a jump start on RISC-V development. It shows how to build a verification environment quickly involving a RISC-V core and required peripherals based on selected applications.
The Six Steps Of RISC-V Processor Verification Including Vector Extensions

Article - Mar 03, 2021 by Larry Lapides

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.
Trends in Functional Verification

Webinar - Mar 02, 2021 by Harry Foster

Adopting proven solutions to achieve functional correctness has become critical. In this talk Harry will explore today’s functional verification landscape and present the latest industry trends.
I'm Excited About Formal...My Journey From Skeptic to Believer

Webinar - Feb 26, 2021 by Neil Johnson

In this session, you will learn the about unlikely journey into formal for a verification engineer who’s spent an entire career using simulation.
A Methodology for Comprehensive CDC Analysis

Webinar - Feb 26, 2021 by Atul Sharma

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
A Methodology for Comprehensive CDC Analysis

Resource (Slides (.PDF)) - Feb 26, 2021 by Atul Sharma

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.
Epilogue: 2020 Study Summary and Key Findings

Resource (Verification Horizons Blog) - Feb 18, 2021 by Harry Foster

This is the last in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
The ABC of Formal Verification

Webinar - Feb 11, 2021 by Dr. Ashish Darbari

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.
Conclusion: Deeper Dive into Non-Trivial Bug Escapes

Resource (Verification Horizons Blog) - Feb 10, 2021 by Harry Foster

Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes. This maturity is likely due to the growing complexity of designs and related efforts to control cost and engineering headcount through the adoption of FPGA design and verification solutions that increase productivity.
Verification Learns a New Language

Resource (Verification Horizons Blog) - Feb 08, 2021 by Ray Salemi

Are SystemVerilog or VHDL the only languages for testbench design? What about Python?
I Didn't Know Visualizer Could Do that

Resource (Slides (.PDF)) - Feb 05, 2021 by Rich Edelman
Part 12: IC/ASIC Verification Results Trends

Resource (Verification Horizons Blog) - Feb 03, 2021 by Harry Foster

In this blog, I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs. A metric often tracks to measure efficiency is ASIC/IC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 68 percent of IC/ASIC projects were behind schedule.
ISO 26262 Creating an Optimal Safety Architecture

Resource (Slides (.PDF)) - Feb 02, 2021 by Jacob Wiltgen
ISO 26262: Creating an Optimal Safety Architecture

Session - Feb 02, 2021 by Jake Wiltgen

In this session, you will gain an understanding of the core challenges defining an optimal safety architecture. This session will describe the pros and cons of various safety features deployed within a larger safety architecture. Additionally, a workflow and methodology will be described which guides the creation and also validates the safety architecture prior to executing an expensive fault campaign.
Part 11: IC/ASIC Power Management Trends

Resource (Verification Horizons Blog) - Jan 27, 2021 by Harry Foster

In this blog, I focus on low power trends. In figure 11-1, we see that the percentage of design projects who actively manage power by design size. The data suggest that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.
Mil/Aero Analysis Functional Verification Study - 2020

Resource (Paper (.PDF)) - Jan 20, 2021 by Harry Foster
Part 9: ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Jan 14, 2021 by Harry Foster

In this blog I examine IC/ASIC project verification technology adoption trends. The IC/ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of IC/ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2020 as shown in Figure 9-1.
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Jan 06, 2021 by Harry Foster

In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity. Figure 8-1 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product.
MathWorks® Integration

Resource (Slides (.PDF)) - Dec 29, 2020 by Bob Oden

In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.