New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

Register Now!

On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Available Now!

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Register Now!
SIEMENS Verification Academy

Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.

A higher level of access is required to view this content. Upgrade your account to view.

Full-access members only

Register your account to view Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.

Register account