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Episode 1: The Current Trends in ASIC Design and Verification
Resource (Podcast) - Nov 09, 2022 Harry Foster
In this episode, you’ll learn about current ASIC hardware design and verification trends. You’ll also learn about some of the factors that are increasing ASIC’s complexity. Additionally, Harry will share some research data demonstrating the impact of increased complexity on the industry.
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Episode 2: The Current Trends in ASIC Design Verification Technology
Resource (Podcast) - Nov 09, 2022 Harry Foster
In this episode, you’ll learn about current trends in the adoption of verification technology. You’ll also learn about why there has been little change in the languages being used in verification. Additionally, you’ll learn about the impact that verification technology is having on the industry.
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Part 4: FPGA Verification Effort Trends (Continued)
Resource (Verification Horizons Blog) - Nov 06, 2022 Harry Foster
In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 4-1. In 2022, design engineers spent on average 58 percent of their time involved in design activities and 42 percent of their time in verification.
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Episode 2: The Current Trends in FPGA Verification
Resource (Podcast) - Nov 02, 2022 Harry Foster
In this episode, you’ll learn about current trends in FPGA verification and what is necessitating changes. You’ll also learn about the steps being taken to handle the increased FPGA verification complexity.
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Questa Design Solutions as a Sleep Aid
Webinar - Nov 02, 2022 Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Questa Design Solutions as a Sleep Aid
Resource (Slides (.PDF)) - Nov 02, 2022 Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Part 3: FPGA Verification Effort Trends
Resource (Verification Horizons Blog) - Oct 30, 2022 Harry Foster
In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.
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ISO 26262…the Tale of Transient and Permanent Faults
Resource (Verification Horizons Blog) - Oct 27, 2022 Jacob Wiltgen
Are you designing to the ISO 26262 standard and trying to decide if your design is safe from random hardware faults? If so, are you trying to figure out those annoying safety metrics (PMHF, SPFM and LFM)? If so, you are also undoubtedly weighing both transient and permanent faults.
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Episode 1: The Growing Complexity in Field Programmable Gate Arrays (FPGA)
Resource (Podcast) - Oct 26, 2022 Harry Foster
In this podcast episode, you’ll learn about current trends in FPGA design and what is necessitating changes. You’ll also learn about the impact of increased FPGA complexity on verification and production cost. Additionally, you’ll hear about how FPGA projects are being impacted.
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CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Resource (Slides (.PDF)) - Oct 25, 2022 Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Webinar - Oct 25, 2022 Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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Part 2: FPGA Verification Effectiveness Trends
Resource (Verification Horizons Blog) - Oct 24, 2022 Harry Foster
In this blog, I present the findings from our new study related how successful FPGA projects are in terms of verification effectiveness. IC/ASIC projects have often used the metric “number of required spins before production” as a benchmark to assess a project’s verification effectiveness. Historically, about 30% of IC/ASIC projects achieve first silicon success, and most successful designs are productized on the second silicon spin. Unfortunately, FPGA projects have no equivalent metric.
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Industry Data and Surveys
Track - Oct 24, 2022 Harry Foster
Every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent survey of design verification practices around the world. Results of the functional verification study demonstrate an ongoing convergence of design and verification practices toward a common methodology.
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Formal and the Next Normal
Webinar - Oct 19, 2022 Joe Hupcey
In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
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Dig a Pool of Specialized SystemVerilog Classes
Resource (Verification Horizons Blog) - Oct 17, 2022 Chris Spear
SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if you want to reuse the methods but change the type of properties? Use a parameter and specialize it!
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Part 1: FPGA Design Trends
Resource (Verification Horizons Blog) - Oct 16, 2022 Harry Foster
In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period.
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Prologue: The 2022 Wilson Research Group Functional Verification Study
Resource (Verification Horizons Blog) - Oct 10, 2022 Harry Foster
This is the first in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. Similar to my previous 2020 Wilson Research Group functional verification study blog series , I plan to separate the discussion by FPGA and IC/ASIC findings. Study Overview The study results presented in this blog series are a continuation of a series of industry studies on functional verification that began in 2007 and continued biennially starting in 2010.
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UVM Testbench Debug – A Day At The Beach – Right?
Resource (Verification Horizons Blog) - Oct 04, 2022 Rich Edelman
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the beach. At my house, summer is definitely over but we’re still getting a declining number of “summer hot” days – without the benefit of the beach. This summer we spent some time doing nothing much at the beach. But it’s hard to shut it all down – I kept thinking about how debug is like a day at the beach…
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Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs
Webinar - Sep 30, 2022 Martin Rowe
In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.
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SystemVerilog: Implicit handles
Resource (Verification Horizons Blog) - Sep 06, 2022 Chris Spear
How can your routine access a class-level variable when there is a local variable with the same name? This often happens when a set() method or the constructor initializes a class property with an argument. A common style is to give the argument the same name as the class property, such as weight shown here. If the assignment was just “weight = weight”, both names would refer to the closest definition, which is the routine argument.
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SystemVerilog: Class Member Visibility
Resource (Verification Horizons Blog) - Aug 29, 2022 Chris Spear
With most OOP languages, you are encouraged to limit direct access to class members, especially properties (variables), to prevent this sort of bug. The recommendation is to create set() and get() methods. In SystemVerilog, the default access is public, which means that other code can read and write properties and call all methods (routines). There is no keyword for this behavior.
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UVM Framework Release 2022.3
Resource (Tarball) - Aug 15, 2022 Bob Oden
General Updates: Out of order race scoreboard added to uvmf_base_pkg Added ability to set base class for subset of UVMF base classes using BASE_T parameter Added uvmf_virtual_sequence_base and uvmf_virtual_sequencer_base to uvmf_base_pkg.
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Finding Data
Resource (Verification Horizons Blog) - Jul 28, 2022 Rich Edelman
Another weekend of weeding. Dark Star – Ceanothus – A California Lilac in the picture. (Not a weed). But enough with weeding. What are some debug techniques that I can use in everyday life? In this installment of using Visualizer Debug Environment – “Finding Data” will offer useful debug and visualizations for everyday debug.
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How to Use Checklists for DO-254 Verification
Resource (Verification Horizons Blog) - Jul 07, 2022 Tammy Reeve - Patmos Engineering Services
Document DO-254 provides aerospace and defense companies with the needed guidance to develop and verify airborne electronic hardware. Some clients use products like Siemens’ Questa to fulfill vital verification objectives of DO-254 such as hardware behavior simulation and code coverage as a means for elemental analysis. But did you know a simple checklist can also be an effective DO-254 verification tool?
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Back to the Future with Formal Property Checking
Article - Jul 05, 2022 Harry Foster
Back in 2010, I decided that instead of documenting a specific instance of applying formal property checking on a particular design, I would step back and look at the formal property checking process holistically. The goal was to define a set of repeatable steps that could be applied to any design. Fast forward to today, where I update the original by keeping the content that is still relevant and augmenting it with the new philosophies, methodologies, and technologies that have evolved since.