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Application of AI/ML to Optimize Fault Simulation Coverage
Article - Dec 01, 2022 Avnita Pal and Sastry Puranapanda - Silicon Interfaces®
Fault simulation replicates the typical sources of failures and analyzes them using the leading EDA tool. Testing is structured using fault simulator techniques to gain insight into fault effects and ensure defect coverage and quality testing are achieved. This article is based on standard fault Simulation and standard fault simulation techniques used in industry and applies intelligence and learning algorithms to reduce simulation cycles.
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Understanding and Using Immediate Assertions
Article - Dec 01, 2022 Ben Cohen
Immediate assertions are typically used to verify that expressions are within their required bounds, such as no overreach of the value of a counter or an illegal condition such a write without an enable. The action block is typically used for debug to display more information as to the cause of the error. However, immediate assertions can also be used to modify testbench variables for use in monitors or in other assertions, or to change the course of a testbench flow.
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Union of SoC Design & Functional Safety Flow
Webinar - Nov 30, 2022 Vedant Garg
In this session, you will learn how Siemens’ safety verification tools and unique methodologies are easy to adopt, and how they accelerate each development phase.
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Part 7: IC/ASIC Design Trends
Resource (Verification Horizons Blog) - Nov 28, 2022 Harry Foster
Now my plan is to shift the focus in this series of blogs from FPGA trends to IC/ASIC trends. And specifically in this blog, I present trends related to various aspects of design to illustrate growing design complexity. Fig. 7-1 shows the trends from the 2012 through the 2022 studies in terms of active IC/ASIC design project by design sizes (gates of logic and datapath, excluding memories).
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Part 6: FPGA Verification Language and Library Adoption Trends
Resource (Verification Horizons Blog) - Nov 21, 2022 Harry Foster
In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
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Functional Verification Study - 2022
Session - Nov 16, 2022 Harry Foster
In this session, Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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Part 5: FPGA Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - Nov 13, 2022 Harry Foster
In this blog I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?”
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Episode 1: The Current Trends in ASIC Design and Verification
Resource (Podcast) - Nov 09, 2022 Harry Foster
In this episode, you’ll learn about current ASIC hardware design and verification trends. You’ll also learn about some of the factors that are increasing ASIC’s complexity. Additionally, Harry will share some research data demonstrating the impact of increased complexity on the industry.
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Episode 2: The Current Trends in ASIC Design Verification Technology
Resource (Podcast) - Nov 09, 2022 Harry Foster
In this episode, you’ll learn about current trends in the adoption of verification technology. You’ll also learn about why there has been little change in the languages being used in verification. Additionally, you’ll learn about the impact that verification technology is having on the industry.
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Part 4: FPGA Verification Effort Trends (Continued)
Resource (Verification Horizons Blog) - Nov 06, 2022 Harry Foster
In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 4-1. In 2022, design engineers spent on average 58 percent of their time involved in design activities and 42 percent of their time in verification.
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Episode 2: The Current Trends in FPGA Verification
Resource (Podcast) - Nov 02, 2022 Harry Foster
In this episode, you’ll learn about current trends in FPGA verification and what is necessitating changes. You’ll also learn about the steps being taken to handle the increased FPGA verification complexity.
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Questa Design Solutions as a Sleep Aid
Webinar - Nov 02, 2022 Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Questa Design Solutions as a Sleep Aid
Resource (Slides (.PDF)) - Nov 02, 2022 Vinayak Desai
In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
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Part 3: FPGA Verification Effort Trends
Resource (Verification Horizons Blog) - Oct 30, 2022 Harry Foster
In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…” In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.
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ISO 26262…the Tale of Transient and Permanent Faults
Resource (Verification Horizons Blog) - Oct 27, 2022 Jacob Wiltgen
Are you designing to the ISO 26262 standard and trying to decide if your design is safe from random hardware faults? If so, are you trying to figure out those annoying safety metrics (PMHF, SPFM and LFM)? If so, you are also undoubtedly weighing both transient and permanent faults.
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Episode 1: The Growing Complexity in Field Programmable Gate Arrays (FPGA)
Resource (Podcast) - Oct 26, 2022 Harry Foster
In this podcast episode, you’ll learn about current trends in FPGA design and what is necessitating changes. You’ll also learn about the impact of increased FPGA complexity on verification and production cost. Additionally, you’ll hear about how FPGA projects are being impacted.
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CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Resource (Slides (.PDF)) - Oct 25, 2022 Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Webinar - Oct 25, 2022 Atul Sharma
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently.
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Part 2: FPGA Verification Effectiveness Trends
Resource (Verification Horizons Blog) - Oct 24, 2022 Harry Foster
In this blog, I present the findings from our new study related how successful FPGA projects are in terms of verification effectiveness. IC/ASIC projects have often used the metric “number of required spins before production” as a benchmark to assess a project’s verification effectiveness. Historically, about 30% of IC/ASIC projects achieve first silicon success, and most successful designs are productized on the second silicon spin. Unfortunately, FPGA projects have no equivalent metric.
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Industry Data and Surveys
Track - Oct 24, 2022 Harry Foster
Every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent survey of design verification practices around the world. Results of the functional verification study demonstrate an ongoing convergence of design and verification practices toward a common methodology.
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Formal and the Next Normal
Webinar - Oct 19, 2022 Joe Hupcey
In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
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Dig a Pool of Specialized SystemVerilog Classes
Resource (Verification Horizons Blog) - Oct 17, 2022 Chris Spear
SystemVerilog classes are a great way to encapsulate both variables and the routines that operates on them. What if you want to reuse the methods but change the type of properties? Use a parameter and specialize it!
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Part 1: FPGA Design Trends
Resource (Verification Horizons Blog) - Oct 16, 2022 Harry Foster
In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period.
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Prologue: The 2022 Wilson Research Group Functional Verification Study
Resource (Verification Horizons Blog) - Oct 10, 2022 Harry Foster
This is the first in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. Similar to my previous 2020 Wilson Research Group functional verification study blog series , I plan to separate the discussion by FPGA and IC/ASIC findings. Study Overview The study results presented in this blog series are a continuation of a series of industry studies on functional verification that began in 2007 and continued biennially starting in 2010.
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UVM Testbench Debug – A Day At The Beach – Right?
Resource (Verification Horizons Blog) - Oct 04, 2022 Rich Edelman
Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the beach. At my house, summer is definitely over but we’re still getting a declining number of “summer hot” days – without the benefit of the beach. This summer we spent some time doing nothing much at the beach. But it’s hard to shut it all down – I kept thinking about how debug is like a day at the beach…