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September 2021 - Volume 17 Issue 2 (12)
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Memory Models (10)
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Israel Static & Formal Tech Day (7)
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LLMs (7)
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Metastable (7)
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Flip-Flop (5)
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VA Live 2019 - Westford (5)
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July 2023 - Volume 19 Issue 2 (3)
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2075 Results

  • VA Live - El Segundo: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • VA Live - Westford: Introduction and Welcome

    Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook

    Welcome to Verification Academy Live.

  • Learn about the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

    Resource (Verification Horizons Blog) - Jun 04, 2024 by Joe Hupcey

    The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle to keep up with the latest enhancements and capabilities. Hence, the “PCI SIG” standards organization holds an annual conference for D&V engineers to learn directly from the industry’s PCIe experts via technical training sessions; sharing best practices to ultimately improve product roll-out and interoperability.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Resource (Slides (.PDF)) - Jun 04, 2024 by Rick Schmidt - Siemens EDA

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • Mark your calendar for the 2024 DAC-Chips to Systems Conference

    Resource (Verification Horizons Blog) - May 28, 2024 by Harry Foster

    Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.

  • Questa RDC Assist: Accelerate Reset Closure with AI/ML

    Webinar - May 22, 2024 by Farhad Ahmed

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    Resource (Slides (.PDF)) - May 22, 2024 by Farhad Ahmed

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification

    Resource (Slides (.PDF)) - May 21, 2024 by Chris Giles

    Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

  • Functional Monitoring: From Lab to In-Life

    Resource (Slides (.PDF)) - May 21, 2024 by Fady Abushahla - Siemens EDA

    In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.

  • Navigating Reset Domain Crossings to Safety in Complex SoCs

    Resource (Verification Horizons Blog) - May 21, 2024 by Reetika - Siemens EDA

    As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management blocks, and DSP cores are proliferating. This surge necessitates a shift towards intricate power and performance management strategies, often incorporating several asynchronous and soft resets.

  • Beyond Speed: Unlocking Productivity in Simulation and Debug

    Resource (Slides (.PDF)) - May 21, 2024 by Moses Satyasekaran

    Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

    Resource (Slides (.PDF)) - May 21, 2024 by Austin Mam

    This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Resource (Slides (.PDF)) - May 21, 2024 by Kamlesh Mulchandani

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • Developing “Safe” AI Hardware

    Conference - May 07, 2024 by Shaumik Ganguly - Continental

    In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.

  • Coverage Closure Acceleration Using Collaborative Verification IQ Tool

    Conference - May 07, 2024 by Suma Ramanand - Nokia

    In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.

  • Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

    Conference - May 07, 2024 by Ariel Ansbacher - Veriest

    In this session you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.

  • Extraction of VC File for Physical Macro From Top VC File

    Conference - May 07, 2024 by Nirav Patel - Arm

    A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.

  • Improving Simulation Performance Utilizing the Visualizer Profiler

    Conference - May 07, 2024 by George Lloyd - Arm

    In this session you will learn how Visualizer Profiler was used to identify areas for improvement within Arm VIP components and how these issues were addressed, reducing simulation time that were achieved due to these optimizations.

  • Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches

    Conference - May 07, 2024 by Espen Tallaksen - EmLogic

    In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).

  • Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend

    Conference - May 07, 2024 by Mihajlo Katona - Veriest

    In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method.

  • New AI Horizons in Static & Formal Verification

    Resource (Recording) - Apr 24, 2024 by Dan Yu

  • New AI Horizons in Static & Formal Verification

    Resource (Slides (.PDF)) - Apr 24, 2024 by Dan Yu

  • Optimizing FPGA Equivalence Checking for A&D Designs

    Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Urish

  • Driving Efficient Execution with Continuous Integration

    Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Campbell

  • Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

    Resource (Slides (.PDF)) - Apr 24, 2024 by Dr. Jonathan Graf