UVM Framework
In this track you will learn more about UVM Framework and how it that provides a reusable UVM methodology and code generator for rapid testbench generation.
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UVMF Releases
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UVMF Release Notes
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Sessions
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UVMF - Series Introduction
In this session, you are introduced to the UVM Framework and the list of sessions that comprise this video track. -
UVMF - Overview
In this session, you will learn what the UVM Framework is, the functionality it provides, its testbench architecture, and available documentation and support. -
Code Generation Introduction
In this session, you will learn why code generation can be a powerful tool and how to take advantage of it for the purposes of quickly producing a UVMF-based testbench. -
Agents: Architecture and Operation
In this session, you will learn about components within a protocol agent and its associated bus functional models and the roles and responsibilities of these components including the abstraction level they operate at. -
Interface Code Generation
In this session, you will learn the steps needed to produce code for an UVMF Interface using the generator. -
Environments: Architecture and Operation
In this session, you will learn the roles and responsibilities of an environment within a simulation. -
Scoreboards and Predictors
In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured. -
Questa Verification IP Integration
In this session, you will learn how to integrate Questa Verification IP within your UVMF testbench. -
Environment Code Generation
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment. -
Testbench: Architecture and Operation
In this session, you will learn about the architecture of a UVMF testbench and directory structure. -
Bench Code Generation
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Bench and what parts of the generated output that you’ll need to modify afterwards. -
Instantiating the DUT
In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench. -
Adding Tests and Sequences
In this session, you will learn how to add sequences and test cases to a UVMF testbench using the example derived test and extended top level virtual sequence. -
Sequence Categories
In this session, you will learn the roles and responsibilities of the sequence categories and that sequences within UVMF are divided into three categories: interface, environment, and testbench. -
UVMF & Emulation
The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there. -
Running Simulations
In this session, you will learn how to run individual UVMF simulations in both batch and debug mode. -
Code Generation Guidelines
In this session, you will be given an overview of the flow used to generate a working simulation using the UVMF code generator. -
Stimulus and Analysis Data Flow
In this session, you will be given an overview of the stimulus and analysis flow within the UVM Framework. -
Code Generation Merging
In this session you will learn about UVMF code generation capabilities that allow you to quickly produce new iterations of generated code that automatically transfer previous manual edits from earlier versions. -
Mathworks Integration
In this session you will learn how the UVMF code generator can automatically integrate blocks created using Mathworks® products. -
Register Model Generation and Integration
In this session, you will be introduced to the generation of a register model as part of a UVMF environment. -
Register Model Generation and Replacement
In this session, you will learn how to produce a UVM register model, applying it to a UVMF testbench. -
Register Adapters, Predictors and Tests
In this session, you will learn how to use register model adapters, predictors, and tests in UVMF. -
UVMF Build/Compile/Run Script Introduction
In this session, you will be introduced to the capabilities and use of the UVMF Build/Compile/Run script. -
Installing Python on Windows
In this session, you will learn how to install Python on a Windows system for use with UVMF scripts. -
Generating UVMF Code on Windows
In this session, you will learn how to use the generation scripts on Windows to produce UVMF testbench source. -
Simulating UVMF Code on Windows
In this session, you will learn how to use the UVMF Build/Compile/Run script on Windows.
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Overview
View all UVM Framework resourcesThe UVM Framework is an open-source package that provides a reusable UVM methodology and code generator that provides rapid testbench generation. The sessions in this track describe the architecture, flow, generation, and use of UVM Framework testbenches.
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Forum Discussion - UVM Framework