Scoreboard evaluating before monitor updates in SystemVerilog testbench (DFF)

SystemVerilog
1

I am building a class-based SystemVerilog testbench with
generator, driver, monitor, and scoreboard (non-UVM).

DUT is a simple D flip-flop with async reset.

Issue:
Scoreboard comparison happens before valid monitored data,
and DUT output q stays 0 even though randomized din is driven.

Output:

time=175, vif.dr_cb.din=0x504, data_drv.din=0x504
drived successfully
** success**
actual=0x0 exp=0x0
Time=185, monitor read the dut signals, din=0x504, rst=0
monitoring ended

It appears that scoreboard evaluates before monitor updates
or before DUT output stabilizes.

Question?
What is the correct way to synchronize driver, monitor,
and scoreboard for a registered DUT like this?

Should scoreboard wait on monitor activity or on a clock edge?

2

it’s hard to answer without seeing any code, but in general, the DUT will have some latency, which means that the actual response transaction coming from the monitor will arrive at the scoreboard AFTER the expected transactiopn coming from your predictor.

This means that your scoreboard needs to implement a queue (or some other means of storage) to hold the expected result until such time as the actual response arrives. Only when both transactions have arrived can it then perform the comparison.

I’m sure there must be coded examples you can find online.

Take a look at the UVM Framework library that you can download from here :

Inside the uvmf_base_pkg\src folder are a number of scoreboard examples

The simplest is the in_order scoreboard, but there are other examples such as the out_of_order scoreboard, race scoreboards, etc