I am building a class-based SystemVerilog testbench with
generator, driver, monitor, and scoreboard (non-UVM).
DUT is a simple D flip-flop with async reset.
Issue:
Scoreboard comparison happens before valid monitored data,
and DUT output q stays 0 even though randomized din is driven.
Output:
time=175, vif.dr_cb.din=0x504, data_drv.din=0x504
drived successfully
** success**
actual=0x0 exp=0x0
Time=185, monitor read the dut signals, din=0x504, rst=0
monitoring ended
It appears that scoreboard evaluates before monitor updates
or before DUT output stabilizes.
Question?
What is the correct way to synchronize driver, monitor,
and scoreboard for a registered DUT like this?
Should scoreboard wait on monitor activity or on a clock edge?