Parameterized Tests
SystemVerilog provides a number of ways to pass changeable values through different code structures. Some changeable values must be fixed at elaboration time, others can be changed at run-time after starting a simulation.
Changeable values fixed at elaboration time are represented using either a SystemVerilog parameter or `define macro. The use of `define macros causes complications in cases of multiple instances of a module or interface where each instance needs a different changeable value.
