Sumit Vishwakarma

Sumit Vishwakarma has over 15 years of experience in the EDA industry including 10 years in AMS and 5 years in digital verification. At Siemens EDA, Sumit is responsible for product management and marketing functions across Siemens EDA’s AMS verification product portfolio driving circuit simulation, mixed-signal, and library characterization platform. Over the years, Sumit has held various roles ranging from design engineer, application engineer and verification specialist at Intel, Springsoft and Synopsys. Before joining Siemens EDA, Sumit was responsible to drive the sales and development of Analog/Mixed-Signal simulators and verification and debug platforms at Synopsys. He has published papers in IEEE, DesingCon, DAC, SNUG, U2U and multiple tech articles and blogs on mixed signal verification methodologies. Sumit has a MS in Electrical engineering from Arizona State and Management Science & Engineering PD from Stanford. He is a vivid digital artist and love teaching art to kids.

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New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

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VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Sumit Vishwakarma

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