PCIe Gen7 Webinar

Wednesday, Mar 26th-10:00 AM PDT

Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs

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Debug Webinar

Thursday, Apr 03rd-8:00 AM PDT

Accelerate Root Cause Analysis & Reduce Debug Turnaround Time with Questa VIQ Regression Navigator

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Simulation Webinar

Wednesday, Apr 16th-8:00 AM PDT

Faster Debug Using QuestaSim Interactive Coverage Analysis

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FPGA Design Webinar

Wednesday, Apr 23rd-8:00 AM PDT

Securing your FPGA Design from RTL through to the Bitstream

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Avery VIP Webinar

Wednesday, Apr 30th-10:00 AM PDT

Ethernet 1.6T, Infiniband, UALink & UEC Verification for Next-Gen Connectivity

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SIEMENS Verification Academy

Joe Hupcey

oe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.

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