New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Fremont, CA

Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Register Now!

FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Register Now!

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Register Now!
SIEMENS Verification Academy

Darron May

Darron May has over 30 years of experience in the electronics industry including board, FPGA, and chip design & verification, pre and post sales support, applications, consulting and technical marketing. As a Product Manager in the Design Verification Technology Division of Siemens EDA, Mr. May has most recently been focused on architecting Verification Management solutions based on customer requirements and driving the deployment of the tools worldwide. Prior to Mentor Graphics, Mr. May has held positions in the engineering and applications management in the Datacoms and EDA industries, for Racal Datacom, Racal Research, Model Technology Inc., and through distribution including Synplicity, Summit Design, TSSI, InterHDL, and Simucad. Mr. May holds an HND in Electronic Engineering from Basingstoke college of technology.

Content by Darron May

Filters

Filter By

Subject Matter Experts