New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Darron May

Darron May has over 30 years of experience in the electronics industry including board, FPGA, and chip design & verification, pre and post sales support, applications, consulting and technical marketing. As a Product Manager in the Design Verification Technology Division of Siemens EDA, Mr. May has most recently been focused on architecting Verification Management solutions based on customer requirements and driving the deployment of the tools worldwide. Prior to Mentor Graphics, Mr. May has held positions in the engineering and applications management in the Datacoms and EDA industries, for Racal Datacom, Racal Research, Model Technology Inc., and through distribution including Synplicity, Summit Design, TSSI, InterHDL, and Simucad. Mr. May holds an HND in Electronic Engineering from Basingstoke college of technology.

Content by Darron May

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