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June 2015

Starting Formal Right from Formal Test Planning
Formal Verification Jun 06, 2015 Jin Zhang Article
Intelligent Testbench Automation with UVM and Questa
Simulation Jun 06, 2015 Marcela Simkova, Neil Hand - Codasip Article
Unit Testing Your Way to a Reliable Testbench
Simulation Jun 06, 2015 Neil Johnson Article
Hardware Emulation: Three Decades of Evolution – Part II
Acceleration Jun 06, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article
Accelerating RTL Simulation Techniques
Simulation Jun 06, 2015 Lior Grinzaig - Marvell Article
Emulation Based Approach to ISO 26262 Compliant Processors Design
Functional Safety Jun 06, 2015 David Kaushinsky - Siemens Eda Article
Resolving the Limitations of a Traditional VIP for PHY Verification
Verification IP Jun 06, 2015 Amit Tanwar, Manoj Manu - Siemens Eda Article

March 2015

Does Design Size Influence First Silicon Success?
Planning, Measurement and Analysis Mar 11, 2015 Harry Foster Article
Successive Refinement: A Methodology for Incremental Specification of Power Intent
Low Power Mar 11, 2015 Adnan Khan, John Biggs & Eamonn Quigley - Arm Article
Power Aware RTL Verification of USB 3.0 IPs
Low Power Mar 11, 2015 Gayathri Sn, Badrinath Ramachandra - L&T Technology Services Limited Article
Hardware Emulation: Three Decades of Evolution
Acceleration Mar 11, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article
Evolving the Use of Formal Model Checking in SoC Design Verification
Formal Verification Mar 11, 2015 Ram Narayan Article
Small, Maintainable Tests
UVM - Universal Verification Methodology Mar 11, 2015 Ashley Winn - Sondrel Ic Design Services Article
Functional Coverage Development Tips: Do’s and Don'ts
Coverage Mar 11, 2015 Samrat Patel, Vipul Patel - Einfochips Article

November 2014

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide
Verification IP Nov 01, 2014 Prashant Dixit - Siemens Eda Article
Fast Track to Productivity Using Questa Verification IP
Verification IP Nov 01, 2014 Dave Aerne Article
Cache Coherent Interface Verification IP
Verification IP Nov 01, 2014 Amit Kumar Jain - Siemens Eda Article
Hey You, Design Engineer!
SystemVerilog Nov 01, 2014 Josh Rensch - Siemens Eda Article
Please! Can Someone Make UVM Easier to Use?
UVM - Universal Verification Methodology Nov 01, 2014 Rich Edelman Article
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
UVM - Universal Verification Methodology Nov 01, 2014 Sundar Raman Arunachalam - Verikwest Systems Article
Increase Verification Productivity with Questa UVM Debug
Debug Nov 01, 2014 Dr. Mike Bartley Article

June 2014

Best Practices for FPGA and ASIC Development
FPGA Verification Jun 16, 2014 Josh Rensch - Siemens Eda Article
Visualizer Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!
Debug Jun 16, 2014 Rich Edelman Article
Optimizing Emulator Utilization
Acceleration Jun 16, 2014 Russell Klein Article
MIPI LLI Verification using Questa Verification IP
Verification IP Jun 16, 2014 Vaibhav Gupta - Siemens Eda Article

New White Papers!

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QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

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Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

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Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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