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February 2016

Software-Driven Testing of AXI Bus in a Dual Core ARM® System
Standards Feb 29, 2016 Mark Olen Article

November 2015

Memories Are Made Like This
Verification IP Nov 01, 2015 Mark Peryer Article
A New Stimulus Model for CPU Instruction Sets
Coverage Nov 01, 2015 Staffan Berg, Mike Andrews - Siemens Eda Article
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
Debug Nov 01, 2015 Eric Rentschler - Siemens Eda Article
Hardware Emulation: Three Decades of Evolution - Part III
Acceleration Nov 01, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article
QVIP Provides Thoroughness in Verification
Verification IP Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd. Article
A Generic UVM Scoreboard
UVM - Universal Verification Methodology Nov 01, 2015 Jacob Andersen, Kevin Seffensen, Peter Jensen - Syosil Aps Article

September 2015

Better Living Through Better Class-Based SystemVerilog Debug
Simulation Sep 02, 2015 Rich Edelman Article
Relieving the Parameterized Coverage Headache
Standards Sep 02, 2015 Mike Horn Article
Targeting Internal-State Scenarios in an Uncertain World
Standards Sep 02, 2015 Matthew Ballance Article
Is Intelligent Testbench Automation For You?
Standards Sep 02, 2015 Mark Olen Article
VHDL-2008: Why It Matters
Standards Sep 02, 2015 Jim Lewis Article
Improving Analog/Mixed-Signal Verification Productivity
Analog Mixed-Signal Sep 02, 2015 Ahmed Eisawy Article
Maximum Productivity with Verification IP
Simulation Sep 02, 2015 Raghu Ardeishar Article
Caching in on Analysis
Standards Sep 02, 2015 Mark Peryer Article
Portable VHDL Testbench Automation with Intelligent Testbench Automation
Standards Sep 02, 2015 Matthew Ballance Article
Please! Can Someone Make UVM Easier to Use?
Standards Sep 02, 2015 Raghu Ardeishar Article
Evolution of UPF: Getting Better All the Time
Standards Sep 01, 2015 Erich Marschner Article

July 2015

Automated Generation of Functional Coverage Metrics for Input Stimulus
Standards Jul 01, 2015 Verification Horizons Article

June 2015

Automating the Capture of Assertion Verification Results for DO-254
Functional Safety Jun 06, 2015 Vipul Patel - Einfochips Article
DO-254 Testing of High-Speed FPGA Interfaces
Functional Safety Jun 06, 2015 Nir Weintroub, Sani Jabsheh - Verisense Article
Formal and Assertion-Based Verification of MBIST MCPs
Assertions Jun 06, 2015 Ajay Daga - Fishtail Design Automation Article
Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
SystemVerilog Jun 06, 2015 Tao Jia, Jack Erickson - Mathworks Article
Starting Formal Right from Formal Test Planning
Formal Verification Jun 06, 2015 Jin Zhang Article
Intelligent Testbench Automation with UVM and Questa
Simulation Jun 06, 2015 Marcela Simkova, Neil Hand - Codasip Article

User2User - Santa Clara

Tuesday, May 20th-8:00 AM PDT

Check out the User2User North America 2025 conference session catalog and plan the sessions you'll attend.

Productivity Webinar

Wednesday, May 21st-8:00 AM PDT

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Traceability Webinar

Wednesday, May 28th-8:00 AM PDT

Streamlining Requirements Traceability Using Questa Verification IQ Testplan Author

Verification Academy Live

Tuesday, Jun 03rd-6:30 AM PDT

Hudson, MA | American Heritage Museum

Verification Academy Live

Thursday, Jun 05th-7:30 AM PDT

Huntsville, AL | Siemens Training Center

Coverage Webinar

Wednesday, Jun 18th-8:00 AM PDT

Accelerating Functional Coverage with Questa One CX

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