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January 2013

Overview to AMS Configuration
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Improve AMS Verification Performance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Modeling Guidance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Modeling Abstraction
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Engines
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to Improve AMS Performance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
VHDL-2008 Overview
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Testbench Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
RTL Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Operator Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Package Type Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Fixed Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Floating Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
VHDL-2008 Why It Matters
VHDL 2008 Jan 17, 2013 Jim Lewis Track

November 2012

Effectively Modeling and Analyzing Coverage
Coverage Nov 15, 2012 Tom Fitzpatrick Webinar

September 2012

UVM 1.1c Class Reference
UVM - Universal Verification Methodology Sep 19, 2012 html
More UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Protocol Layering
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Introduction to UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
C-Based Stimulus for UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
UVM Debug
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Scoreboards and Results Predictors in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
OVM to UVM Migration
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Customization in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Improving FPGA Debugging with Assertions
FPGA Verification Sep 10, 2012 Harry Foster Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag sata

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