New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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SIEMENS Verification Academy

Verification with Multi-core Parallel Simulations: Have You Found Your Sweet Spot Yet?

This paper is aimed at verification engineers looking to improve the productivity of their verification flow and to understand where multi-core simulations can provide maximum benefit. Successful multi-core parallel simulations depend on a variety of related design factors, which can be difficult to understand and sort out. With suitable design applications, it is possible to significantly save verification cycles.

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