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June 2022

Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman Paper
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf

September 2021

Questa Lint: Find and Fix RTL Issues
Questa Design Solutions Sep 14, 2021 Tom Carlstedt-Duke Demo

August 2021

UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
UVM Framework Aug 05, 2021 Pedram Riahi - Raytheon Conference

May 2021

Introduction to UVM
UVM - Universal Verification Methodology May 28, 2021 Tom Fitzpatrick Session
Connecting Env to DUT
UVM - Universal Verification Methodology May 28, 2021 Tom Fitzpatrick Session
Architecting a UVM Testbench
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Architecting a UVM Testbench
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Advanced UVM
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Track

April 2021

Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi Webinar
Practical Flows for Continuous Integration: Making the Most of Your EDA Tools
Questa Design Solutions Mar 16, 2021 Neil Johnson Webinar

December 2020

MathWorks® Integration
UVM Framework Dec 29, 2020 Bob Oden pdf
MathWorks® Integration
UVM Framework Dec 29, 2020 Bob Oden Session
Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Dec 22, 2020 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 16, 2020 Harry Foster link

October 2020

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
Debug Oct 27, 2020 Jason Polychronopoulos Webinar

June 2020

Better UVM Debug with Visualizer
Debug Jun 02, 2020 Rich Edelman Webinar

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