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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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July 2022 - Volume 18 Issue 2 (10)

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June 2012 - Volume 8 Issue 2 (9)

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June 2018 - Volume 14 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

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XML (8)

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Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

Layering (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

Order Property Pattern (7)

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VA Live 2023 - Huntsville (7)

Windows (7)

AEH (6)

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Appendix (6)

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Bugged Out Podcast (6)

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Creating and Using a Test Plan (6)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Defect Coverage (6)

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HDL (6)

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Implicit/Explicit (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

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Random Faults (6)

Respins (6)

SFV (6)

Semiconductor (6)

Slave (6)

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Stimulus Free Verification (6)

Syntax (6)

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Test Plan (6)

Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

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Visualization (6)

X-Effects (6)

YAML (6)

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Advance Your Verification Methodology (5)

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DAC 2024 (5)

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December 2019 - Volume 15 Issue 3 (5)

Design Cycle (5)

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February 2019 - Volume 15 Issue 1 (5)

Formal Methods (5)

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HBM (5)

HBM4 (5)

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IDE (5)

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Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

Model Context Protocol (5)

NVM Express (5)

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Phases (5)

Precedence (5)

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Quirky (5)

Repository (5)

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Unified Coverage Database (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

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Verbose (5)

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5G (4)

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DVFS (4)

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Deprecated (4)

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DisplayPort (4)

ECO (4)

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Enumeration (4)

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GPU (4)

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Handles (4)

IC Design (4)

ICE Mode (4)

IEEE (4)

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In-Circuit Simulation (4)

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Initial States (4)

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Large Language Models (4)

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Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

PHY (4)

Partitioning (4)

Phase Objections (4)

Plusargs (4)

Power Constraints (4)

Protocol Checkers (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

Race Conditions (4)

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Reset Signal (4)

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Root Cause (4)

SVTB (4)

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Specification Pattern (4)

Stream (4)

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Subscriber (4)

Subsystem (4)

Synergistic Verification (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Toolkit (4)

Trust Verification (4)

UART (4)

UCIS (4)

UEC (4)

UPF 3.0 (4)

UPF 4.0 (4)

USB (4)

Unreachability (4)

Use Models (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

VPM (4)

Vectors (4)

Verification Blueprint (4)

X-Aware (4)

$display (3)

1.2 (3)

AHB (3)

Affect Probability (3)

Airborne Electronic Hardware (3)

Analysis Components (3)

Analysis Port (3)

Application Lifecycle Management (3)

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Autonomous Systems (3)

Base Test (3)

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Boolean (3)

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Built-In Self-Test (3)

CDC Signals (3)

CSI-2 (3)

Case Statements (3)

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Certification (3)

Class Variables (3)

Clock Definitions (3)

Clocking (3)

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Coroutines (3)

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Coverage Data (3)

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Cryptography (3)

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Delay Loops (3)

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Designers (3)

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ESL (3)

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FWHW (3)

Fault Model (3)

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Golden Model (3)

HLV (3)

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Horizontal Reuse (3)

Illegal Bins (3)

Integration Level (3)

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Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

Lane Margining (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

MUX (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observer (3)

Open Architecture (3)

PCI-SIG (3)

PCIe Gen 8 (3)

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QFL (3)

Qrun (3)

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TBX (3)

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UEFI (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

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VHDL-2019 (3)

VIP - 3.1 (3)

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2D/3D (2)

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AutoPDU (2)

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BiQuad (2)

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Bit Flips (2)

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CDC Working Group (2)

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CSI (2)

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Chains (2)

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Coverage Gap (2)

Coverpoint (2)

Critical Storage (2)

Cross Probing (2)

Cutpoint (2)

D-PHY (2)

DFT Sign-Off (2)

DFT Simulation (2)

DPPM (2)

DVCON 2021 (2)

DVCon 2026 (2)

DVCon India (2)

DVIF (2)

Data Mux (2)

Dead Code (2)

Design Checking (2)

Design Configuration (2)

Digital Signal Processing (2)

Domain Configuration (2)

Domain Topologies (2)

Downcasting (2)

Dynamic Checks (2)

ECUs (2)

ENV Package (2)

Elements List (2)

Embedded Software (2)

Enterprise Debug and Analysis (2)

Equalization (2)

Existence (2)

FIT Rate (2)

Facial Recognition (2)

False Path (2)

Fault Scenarios (2)

Finite State Machine (2)

Floating-Point Hardware (2)

Formal Concepts (2)

Formal Simulation (2)

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October 2019

Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara Webinar
Why RDC Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara pdf

September 2019

Questa SLEC Fact Sheet
Formal Verification Sep 30, 2019 Nicolae Tusinschi link
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden Session
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Bob Oden Session
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
A New Approach to Low Power Verification: Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava - Siemens Eda Paper
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf
Using HLS to Accelerate Computer Vision for Autonomous Drive
High-Level Synthesis Aug 20, 2019 pdf
Source Code Download: Fun with UVM Sequences - Coding and Debugging
Standards Aug 20, 2019 tar
Results Checking Strategies with Portable Stimulus
Portable Stimulus Aug 02, 2019 Tom Fitzpatrick pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman Paper

July 2019

Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick Conference
Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick pdf
An Emulation Strategy for AI and ML Designs
Machine Learning Jul 15, 2019 Vijay Chobisa Conference
An Emulation Strategy for AI and ML Designs
Machine Learning Jul 15, 2019 Vijay Chobisa pdf
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide Conference
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf
Streamlining Plan & Requirements Driven Verification
Planning, Measurement and Analysis Jul 12, 2019 pdf

VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

Browse all content in Siemens Verification Academy with the tag hw/sw verification

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