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Solutions

The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
Techniques

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Methodology

All Solutions
Techniques

Design for Test Verification

Safety & Security

Functional Safety

Methodology

Unified Coverage

Design for Test Verification

Accelerating DFT Sign-Off with Questa One

Tackling Emerging DFT Verification Challenges with Questa One

Functional Safety

Functional Safety for ISO 26262

Functional Safety for DO-254

Unified Coverage

Questa One Unified Coverage Solution: Transforming Verification Through Intelligence

Boost Your Verification Productivity with Questa Verification IQ

Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Functional Safety for ISO 26262

Accelerated Assurance with Questa One Functional Safety

Functional Safety for DO-254

Introduction to DO-254
Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
UVM

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Simulation

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Functional Safety

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Questa Design Solutions

Clock-Domain Crossing

Formal Verification

Reset-Domain Crossing

Verification Management & IP

Verification IQ

Verification IP

Verification Planning
Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
UVM

Guidelines & Migration

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Coverage

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UVM

UVM Basics

UVM Testbench

UVM Configuring a Test Environment

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UVM Sequences

UVM Messaging System

UVM Stimulus Techniques

UVM Register Abstraction Layer

UVM Debugging

UVM Connect

Guidelines & Migration

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SystemVerilog Performance

UVM Coding

UVM Performance

UVM 1800.2

UVM 1.2

OVM to UVM

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UVM 1.2

UVM 1.1d

UVM 1.1c

UVM 1.1b

UVM 1.1a

Coverage

Coverage Metrics and Process (Theory)

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Verification Horizons Blog

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

DFT Verification: Tackling the Evolving Challenges

Closing the Gap in Software Skills for Verification Engineers

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Got Coverage?

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Events & Webinars

Siemens EDA at DAC 2025

Siemens EDA Forum Seoul 2025

VA Live 2025

Post Event Archive

osmosis

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Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

Formal Verification

Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Questa Design Solutions

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

Simulation

Accelerating Functional Coverage with Questa One CX

Tackling Emerging DFT Verification Challenges with Questa One

Faster Debug Using QuestaSim Interactive Coverage Analysis

Unlocking the Power of QuestaSim and Visualizer Integration

Productivity in the Questa Simulation Flow

SystemVerilog

Introduction to SystemVerilog Assertions

Generating SVA Properties with Property Assist

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

Verification IP

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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March 2016

Total Recall: What to Look for in a Memory Model Library
Verification IP Mar 02, 2016 Mark Peryer Article

December 2015

Verification IP Stimulus APIs - Are They Really Easy to Use?
Verification IP Dec 01, 2015 Amit Kumar Jain - Siemens Eda Paper
Verification IP Stimulus APIs - Are They Really Easy to Use?
Verification IP Dec 01, 2015 Amit Kumar Jain - Siemens Eda pdf

November 2015

Leveraging Verification IP (VIP) for Fast & Efficient Verification
Verification IP Nov 25, 2015 Jason Polychronopoulos pdf
Leveraging Verification IP (VIP) for Fast & Efficient Verification
Verification IP Nov 25, 2015 Jason Polychronopoulos Webinar
QVIP Provides Thoroughness in Verification
Verification IP Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd. Article

September 2015

New School Thinking for Fast and Efficient Verification Using EZ-VIP
Verification IP Sep 02, 2015 Jason Polychronopoulos Webinar

March 2015

Power Aware RTL Verification of USB 3.0 IPs
Low Power Mar 11, 2015 Gayathri Sn, Badrinath Ramachandra - L&T Technology Services Limited Article

March 2014

Unidirectional Protocols
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

December 2013

Bus Protocol Coverage
Coverage Dec 04, 2013 Harry Foster Chapter
APB3 Protocol Test Plan
Coverage Dec 04, 2013 Harry Foster Chapter
APB3 Protocol Monitor
Coverage Dec 04, 2013 Harry Foster Chapter

October 2013

Caching in on Analysis
Simulation Oct 01, 2013 Mark Peryer Article
Simulation + Emulation = Verification Success
Acceleration Oct 01, 2013 Lanfranco Salinari, Alberto Allara, And Alessandro Daolio - Stmicroelectronics Article

June 2013

NoC Generic Scoreboard VIP
Verification IP Jun 01, 2013 François Cerisier, Mathieu Maisonneuve - Tvs Article

September 2012

Protocol Layering
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar

October 2011

Modeling SystemC TLM-2.0 Drivers
Acceleration Oct 27, 2011 John Stickley Session
SystemC & TLM-2.0 Monitors and Talkers
Acceleration Oct 27, 2011 John Stickley Session

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