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May 2021

Architecting a UVM Testbench
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Understanding the Factory and Configuration
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Understanding the Factory and Configuration
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Modeling Transactions
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Modeling Transactions
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
How TLM Works
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
How TLM Works
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
The Proper Care and Feeding of Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
The Proper Care and Feeding of Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Layered Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Layered Sequences
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Setting Up the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Writing and Managing Tests
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Writing and Managing Tests
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Setting Up the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Using the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Using the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Register-Based Testing
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Register-Based Testing
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
The Three Witches Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing May 18, 2021 Ping Yeung pdf
Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Machine Learning May 12, 2021 Michael Fingeroff - Siemens Eda pdf
Formal 101 – Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 Mark Eslinger Session
Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 pdf
Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Functional Safety May 04, 2021 Jacob Wiltgen Webinar

April 2021

Low Power Considerations for Verification
Low Power Apr 29, 2021 Rick Koster Webinar

Coverage Webinar

Wednesday, Jun 18th-8:00 AM PDT

Accelerating Functional Coverage with Questa One CX

Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

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May 2021

Architecting a UVM Testbench

Understanding the Factory and Configuration

Understanding the Factory and Configuration

Modeling Transactions

Modeling Transactions

How TLM Works

How TLM Works

The Proper Care and Feeding of Sequences

The Proper Care and Feeding of Sequences

Layered Sequences

Layered Sequences

Setting Up the Register Layer

Writing and Managing Tests

Writing and Managing Tests

Setting Up the Register Layer

Using the Register Layer

Using the Register Layer

Register-Based Testing

Register-Based Testing

The Three Witches Preventing Glitch Nightmares on CDC Paths

Machine Learning at the Edge: Using HLS to Optimize Power and Performance

Formal 101 – Setting Up & Optimizing Constraints

Setting Up & Optimizing Constraints

Optimizing a Fault Campaign for Complex Mixed-Signal Devices

April 2021

Low Power Considerations for Verification