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March 2022

Modeling Analog Devices using SV-RNM
Analog Mixed-Signal Mar 23, 2022 mp4
Path-based UPF Strategies Optimally Manage Power on your Designs
Low Power Mar 23, 2022 pdf
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Video)
UVMC Mar 23, 2022 Vishal Baskar mp4
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Paper)
UVMC Mar 23, 2022 Vishal Baskar pdf
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Poster)
UVMC Mar 23, 2022 Vishal Baskar pdf
Formal 101 - Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 Joe Hupcey Webinar
Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 pdf
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
Questa Design Solutions Mar 10, 2022 Buu Huynh pdf
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
Questa Design Solutions Mar 10, 2022 Buu Huynh Webinar
UVM Framework Release 2022.1
UVM Framework Mar 09, 2022 Bob Oden tar
NVMe-oF – Simple, Invisible Fabric to Cloud Storage
Verification IP Mar 02, 2022 Dhruv Garg - Siemens Eda Article
Getting to Know Visualizer - Part I
Debug Mar 02, 2022 Rich Edelman Article
Enabling Model-Based Design for DO-254 Certification Compliance
Functional Safety Mar 02, 2022 Jacob Wiltgen Article
How Do You “Qualify” Tools for DO-254 Programs?
Functional Safety Mar 02, 2022 Michelle Lange, Tammy Reeve - Patmos Engineering Services Article
Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article
UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Espen Tallaksen - Emlogic Article

February 2022

Equivalence Checking for FPGA
Formal Verification Feb 25, 2022 Martin Rowe Webinar
Achieving High Defect Coverage for Safety Critical and High Reliability Designs
Functional Safety Feb 22, 2022 Lee Harrison Webinar
‘The Dog Ate my RTL’ Doesn’t Work Anymore
Questa Design Solutions Feb 15, 2022 Joe Hupcey Webinar
‘The Dog Ate my RTL’ Doesn’t Work Anymore
Questa Design Solutions Feb 15, 2022 Joe Hupcey pdf
Guidelines to a Successful ISO 26262 Lifecycle
Functional Safety Feb 04, 2022 Jacob Wiltgen link
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
Simulation Feb 02, 2022 Verification Horizons Article

January 2022

Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee pdf
Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee Webinar

DFT Webinar

Thursday, Jun 12th-8:00 AM PDT

Tackling Emerging DFT Verification Challenges with Questa One

Coverage Webinar

Wednesday, Jun 18th-8:00 AM PDT

Accelerating Functional Coverage with Questa One CX

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March 2022

Modeling Analog Devices using SV-RNM

Path-based UPF Strategies Optimally Manage Power on your Designs

Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Video)

Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Paper)

Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Poster)

Formal 101 - Fast, Scalable Formal Verification Made Easy

Fast, Scalable Formal Verification Made Easy

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

UVM Framework Release 2022.1

NVMe-oF – Simple, Invisible Fabric to Cloud Storage

Getting to Know Visualizer - Part I

Enabling Model-Based Design for DO-254 Certification Compliance

How Do You “Qualify” Tools for DO-254 Programs?

Reflections on Users’ Experiences with SVA

A Faster Approach to Co-Simulation Using Questa and VPI

UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification

February 2022

Equivalence Checking for FPGA

Achieving High Defect Coverage for Safety Critical and High Reliability Designs

‘The Dog Ate my RTL’ Doesn’t Work Anymore

‘The Dog Ate my RTL’ Doesn’t Work Anymore

Guidelines to a Successful ISO 26262 Lifecycle

Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench

January 2022

Introduction to Questa Lint and CDC for Designers

Introduction to Questa Lint and CDC for Designers