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Solutions

The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
Techniques

Safety & Security

Methodology

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Techniques

Design for Test Verification

Safety & Security

Functional Safety

Methodology

Unified Coverage

Verification Threading

Design for Test Verification

Accelerating DFT Sign-Off with Questa One

Tackling Emerging DFT Verification Challenges with Questa One

Functional Safety

Functional Safety for ISO 26262

Functional Safety for DO-254

Unified Coverage

Questa One Unified Coverage Solution: Transforming Verification Through Intelligence

Boost Your Verification Productivity with Questa Verification IQ

Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Verification Threading

Questa One VeriThreader: Rethinking Verification Traceability for Modern Systems

Functional Safety for ISO 26262

Accelerated Assurance with Questa One Functional Safety

Functional Safety for DO-254

Introduction to DO-254
Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
UVM

Simulation & Debug

Methodology & Standards

Questa Design Solutions

Verification Management & IP

All Topics
UVM

UVM

UVM Connect

UVM Framework

SystemVerilog

Simulation & Debug

AI/ML

Debug

Simulation

Methodology & Standards

Coverage

FPGA Verification

Functional Safety

Low Power

Portable Stimulus

Questa Design Solutions

Clock-Domain Crossing

Formal Verification

Reset-Domain Crossing

Verification Management & IP

Verification IQ

Verification IP

Verification Planning

UVM

Functional Verification of Digital Logic

Introduction to UVM

UVM Basics

UVM Debug

Advanced UVM

SystemVerilog

SystemVerilog OOP for UVM Verification

Improving Your SystemVerilog Language and UVM Methodology Skills

An Introduction to Unit Testing with SVUnit
Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
Coverage

UVM

Guidelines & Migration

SystemVerilog/SystemC Interoperability

UVM Testbench Acceleration through Co-Emulation

All Cookbooks
Coverage

Coverage Metrics and Process (Theory)

Coverage Examples (Practice)

Appendices

UVM

UVM Basics

UVM Testbench

UVM Configuring a Test Environment

UVM Analysis Components & Techniques

UVM End of Test Mechanisms

UVM Sequences

UVM Messaging System

UVM Register Abstraction Layer

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Class Reference

Code Examples

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UVMC Connections

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UVMC Command API

UVM Testbench Acceleration through Co-Emulation

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Defining an API

Emulation-Ready Testbench Examples

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What is Coverage

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Code Coverage Metrics

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Executable Test Plan Format

Testplan to Functional Coverage

Design For Analysis

Coverage Examples (Practice)

Bus Protocol Coverage

APB3 Protocol Test Plan

APB3 Protocol Monitor

Block Level Functional Coverage Example

UART Example Test Plan

UART Example Covergroups

Datapath Example

BiQuad IIR Filter Test Plan

BiQuad IIR Filter Example Covergroups

System Level Functional Coverage Example

Appendices

Requirements Writing Guidelines

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UVM Factory

UVM Phasing

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UVM Monitor

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UVM Sequence Items

UVM Configuration Database

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Objections

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Coding Guidelines

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PCI Express 8.0: Powering AI, Cloud, and HPC with Transformative Interconnect Technology

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Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

Formal Verification

AI Assisted FPU Verification Using Questa One SFV

HLV: Formal Verification of Synthesizable C++/SystemC Designs and Prove Equivalency with RTL Code

Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Languages

VHDL

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Questa Design Solutions

Resolve Metastability: Improve Your Clock Domain Crossing Verification with Questa CDC

Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

Supercharge your CDC & RDC Analysis with The Power of AI/ML

Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Simulation

Close Coverage Faster with Questa One Sim's Unreachability Analysis

Constrained Randomization and Functional Coverage in Questa One Sim with UVVM

Improving Verification Productivity Using Questa One Sim

Accelerating Functional Coverage with Questa One CX

Tackling Emerging DFT Verification Challenges with Questa One

Faster Debug Using QuestaSim Interactive Coverage Analysis

Unlocking the Power of QuestaSim and Visualizer Integration

Productivity in the Questa Simulation Flow

Verification IP

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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Agentic AI and the Rise of the Design and Verification Scientist

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March 2023

Introduction to SystemVerilog Assertions
SystemVerilog Mar 15, 2023 Chris Crile Webinar

February 2023

A Formal-based Approach for Efficient RISC-V Processor Verification
Formal Verification Feb 24, 2023 Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip Article

December 2022

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 26, 2022 Harry Foster link
Make Formal Simple and Easy-to-Use with Generated Assertion IP
Formal Verification Dec 08, 2022 Tobias Ludwig - Lubis Eda pdf
Make Formal Simple and Easy-to-Use with Generated Assertion IP
Formal Verification Dec 08, 2022 Tobias Ludwig - Lubis Eda mp4
Understanding and Using Immediate Assertions
Assertions Dec 01, 2022 Ben Cohen Article

November 2022

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Nov 28, 2022 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Nov 21, 2022 Harry Foster link

July 2022

Reflections on Users’ Experiences with SVA - Part II
SystemVerilog Jul 05, 2022 Ben Cohen Article
Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

March 2022

Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article

October 2021

CDC Philosophy: The Existential Questions of Constraints, Waivers, and Truth
Clock-Domain Crossing Oct 12, 2021 Kurt Takara Webinar
CDC Philosophy: The existential questions of constraints, waivers, and truth
Clock-Domain Crossing Oct 12, 2021 Kurt Takara pdf

December 2020

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Dec 22, 2020 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Dec 16, 2020 Harry Foster link

July 2020

Formal is the New Normal - Deploy These FV Apps in Your Next Project
Formal Verification Jul 19, 2020 Ajeetha Kumari, Hemamalini Sundaram, And Darshan Ballari, Verifworks, Llc And Cvc Pvt., Ltd. Article
Understanding the SVA Engine Using the Fork-Join Model
SystemVerilog Jul 19, 2020 Ben Cohen Article

June 2020

Deadlock Verification for Dummies: The Easy Way Using SVA and Formal
Formal Verification Jun 02, 2020 Mark Eslinger Webinar

January 2020

Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Jan 20, 2020 Harry Foster link

July 2019

Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps
Low Power Jul 07, 2019 Madhur Bhargava - Siemens Eda Paper
Moving Beyond Assertions: An Innovative Approach to Low Power Checking Using UPF Tcl Apps
Low Power Jul 07, 2019 Madhur Bhargava - Siemens Eda pdf

June 2019

Formal Bug Hunting with “River Fishing” Techniques
Formal Verification Jun 03, 2019 Mark Eslinger Article

February 2019

Simplifying Assertion Validation Using UVM Callbacks
Assertions Feb 25, 2019 Arushi Jain - Siemens Eda Article
Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Feb 14, 2019 Harry Foster link

January 2019

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Jan 22, 2019 Harry Foster link

26–50 of 112

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