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The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
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Coverage Closure Acceleration Using Collaborative Verification IQ Tool

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Accelerated Assurance with Questa One Functional Safety

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Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

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Accellera announces fee-free availability of IEEE Std. 1801™-2024

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Coverage

Accelerating Functional Coverage with Questa One CX

Simulation

Tackling Emerging DFT Verification Challenges with Questa One

Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

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Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Questa Design Solutions

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

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Introduction to SystemVerilog Assertions

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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March 2017

Testbench Automation - Testbench
UVM Framework Mar 17, 2017 Matthew Ballance Webinar
Testbench Automation - Interfaces
UVM Framework Mar 17, 2017 Bob Oden Webinar
Use Formal to Check Logic Faults
Formal Verification Mar 17, 2017 Mark Eslinger Webinar

December 2016

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara Webinar
How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
Formal Verification Dec 05, 2016 Mark Eslinger Webinar

November 2016

FPGA Prototyping: Maximize Your Enterprise Debug Productivity
Debug Nov 11, 2016 Stephen Bailey Webinar
Industry Trends in Today’s Functional Verification Landscape
Planning, Measurement and Analysis Nov 11, 2016 Harry Foster Webinar
Enterprise Verification Debug and Analysis
Debug Nov 11, 2016 Stephen Bailey Webinar
System Level Debug & Analysis
Debug Nov 11, 2016 Gordon Allan Webinar
Enterprise Debug for Formal
Formal Verification Nov 11, 2016 Joe Hupcey Webinar
Enterprise Debug for Simulation
Debug Nov 11, 2016 Moses Satyasekaran Webinar

September 2016

Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
UVM - Universal Verification Methodology Sep 09, 2016 Gordon Allan Webinar

August 2016

Staying Competitive with Advanced FPGA Verification
FPGA Verification Aug 10, 2016 Bryan Ramirez Webinar

November 2015

UVM Framework – Create a UVM Environment in Less than an Hour
UVM Framework Nov 25, 2015 Bob Oden Webinar
Leveraging Verification IP (VIP) for Fast & Efficient Verification
Verification IP Nov 25, 2015 Jason Polychronopoulos Webinar

September 2015

Low Power Verification Techniques
Low Power Sep 23, 2015 Ellie Burns Webinar
New School Thinking for Fast and Efficient Verification Using EZ-VIP
Verification IP Sep 02, 2015 Jason Polychronopoulos Webinar
New School Regression Control
Verification Management Sep 01, 2015 Darron May Webinar

August 2015

Evolution of Debug
Debug Aug 25, 2015 Gordon Allan Webinar

July 2015

New School Connectivity Checking
Formal Verification Jul 01, 2015 Mark Eslinger Webinar

May 2015

New School Coverage Closure
Formal Verification May 29, 2015 Mark Eslinger Webinar

March 2015

UVM Rapid Adoption: A Practical Subset of UVM
UVM - Universal Verification Methodology Mar 31, 2015 Tom Fitzpatrick Webinar

December 2014

Introduction to Questa X-Check
Formal Verification Dec 20, 2014 Doug Smith Webinar

November 2014

Introduction to Questa CDC
Clock-Domain Crossing Nov 12, 2014 Doug Smith Webinar

October 2014

Introduction to Questa CoverCheck
Formal Verification Oct 16, 2014 Doug Smith Webinar

176–200 of 221

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