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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

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December 2017 - Volume 13 Issue 3 (3)

Design Constraints (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

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October 2012 - Volume 8 Issue 3 (3)

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UALink (3)

UVMC 2.3.3 (3)

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VA Live 2019 - Westford (3)

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December 2019 - Volume 15 Issue 3 (2)

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IEEE (2)

IEEE 754 (2)

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ISA (2)

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June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

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March 2014 - Volume 10 Issue 1 (2)

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March 2022 - Volume 18 Issue 1 (2)

Memory-Mapped Registers (2)

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October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

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Execution Trace (1)

Factory (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

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Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

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March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

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November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Observer (1)

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XML (1)

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Show Less

December 2016

What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara Webinar
What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara pdf

November 2016

FPGA Prototyping: Maximize Your Enterprise Debug Productivity
Debug Nov 11, 2016 Stephen Bailey Webinar
Enterprise Verification Debug and Analysis
Debug Nov 11, 2016 Stephen Bailey Webinar
System Level Debug & Analysis
Debug Nov 11, 2016 Gordon Allan Seminar
INs and OUTs of CAN Verification: A Comprehensive UVM-based Solution
Functional Safety Nov 07, 2016 Saumya Agrawal - Siemens Eda Article

September 2016

Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
UVM - Universal Verification Methodology Sep 09, 2016 Gordon Allan Webinar

August 2016

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara Paper
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf

June 2016

Matlab UVM Example (.tgz)
UVM - Universal Verification Methodology Jun 24, 2016 tar
Verifying Safety-Related Systems
Functional Safety Jun 20, 2016 Dr. Mike Bartley pdf
Various Methods for Debugging Software in Emulation
Acceleration Jun 20, 2016 Russell Klein pdf
Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
Functional Safety Jun 01, 2016 Francis Raguin - Barco N.V. Article

April 2016

Classes
SystemVerilog Apr 27, 2016 Dave Rich Session
Classes
SystemVerilog Apr 27, 2016 Dave Rich pdf
Inheritance and Polymorphism
SystemVerilog Apr 27, 2016 Dave Rich Session
Inheritance and Polymorphism
SystemVerilog Apr 27, 2016 Dave Rich pdf
OOP Design Pattern Examples
SystemVerilog Apr 27, 2016 Dave Rich pdf
OOP Design Pattern Examples
SystemVerilog Apr 27, 2016 Dave Rich Session
Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Low Power Apr 13, 2016 Joe Hupcey pdf

March 2016

Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 02, 2016 Saumya Agrawal - Siemens Eda Article
Nine Effective Features of NVMe® Questa Verification IP to Help You Verify PCIe® Based SSD Storage
Verification IP Mar 02, 2016 Saurabh Sharma - Siemens Eda Article
MIPI C-PHY™: Man of the Hour
Verification IP Mar 02, 2016 Yogesh Chaudhary - Siemens Eda Article
Certus™ Silicon Debug: Don’t Prototype Without It
Debug Mar 02, 2016 Doug Amos - Siemens Eda Article
DO-254 Compliant UVM VIP Development
Functional Safety Mar 02, 2016 Ates Berna - Electra Ic Article

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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