Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.
Full-access members only
Register your account to view Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.