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  1. Introduction

    With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.

    Initially, CDC verification for low power designs was run at the gate-level. For larger designs, designers achieve greater efficiencies through abstraction. Here, the abstraction involves running power aware CDC analysis at the RTL instead of the gate-level. Power aware CDC verification at the RTL increases productivity by allowing designers to run the CDC analysis and fix CDC problems earlier in the design cycle to achieve time and resource savings.

    When designers run low power CDC verification at the gate-level, the CDC violations identified would require expensive, late-stage design modifications. In addition, running low power CDC verification at the RTL will allow architects to do what-if analysis by testing power architecture scenarios.

    In this paper, we begin by discussing the low power challenges for CDC design and verification including dynamic frequency and voltage scaling (DVFS). The following section describes the low power CDC verification methods and how these methods address the low power issues. Finally, we review some application examples for low power DVFS CDC verification.

    Low Power Design Challenges

    For most designs, the power logic is not instantiated in the design, so the power intent is absent in the RTL and extracted from the Unified Power Format (UPF) file during synthesis. The UPF is the universal standard for specifying the power control logic and its design connections. This late implementation of the power intent information into the gate-level design may delay the start of power verification until after the gate-level representation is available. When a power-related CDC issue is found late in the design flow, the cost for fixing this bug is higher than if the bug was caught earlier in the design cycle.

  2. Download Paper