Verification Horizons
The advent of new technologies - such as constrained-random data generation, assertion-based verification, coverage-driven verification, and formal model checking to name a few - have changed the way we see functional verification productivity. An advanced verification process enables users to manage the application of these new technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs have been covered.
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Verification Horizons
The Verification Horizons expands upon verification topics to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them.
In addition, the Verification Horizons Blog provides an online forum providing updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
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March 2024
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Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App
Acceleration Mar 01, 2024 Article -
Formal Verification: An Introduction and Exploration of Challenges
Formal Verification Mar 01, 2024 Article -
A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Machine Learning Mar 01, 2024 Article
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July 2023
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Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project
Functional Safety Jun 21, 2023 Article -
Mitigating System Failure Risks by verifying the Safeness of SafeSPI sub-module for the Automotive Industry
Functional Safety Jun 21, 2023 Article
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March 2023
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Big Data Reimagines Verification Predictability and Efficiency
Planning & Analysis Feb 24, 2023 Article -
Democratizing Digital-Centric Mixed-Signal Verification Methodologies
Analog Mixed-Signal Feb 24, 2023 Article -
Lane Margining at Receiver and its Application Through Pipe Message Bus
Verification IP Feb 24, 2023 Article -
The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines
Verification IP Feb 24, 2023 Article -
A Formal-based Approach for Efficient RISC-V Processor Verification
Formal Verification Feb 24, 2023 Article -
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December 2022
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Effective Resource Utilization in PCIe® Gen6: Shared Flow Control
Verification IP Dec 01, 2022 Article -
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July 2022
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The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Article -
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Article -
Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family
Acceleration Jul 05, 2022 Article -
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March 2022
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Enabling Model-Based Design for DO-254 Certification Compliance
Functional Safety Mar 02, 2022 Article -
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UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Article
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September 2021
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What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Article -
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Addressing the Trends and Challenges of Automotive IC Development
Functional Safety Sep 01, 2021 Article -
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Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Acceleration Sep 01, 2021 Article -
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Acceleration Sep 01, 2021 Article -
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March 2021
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What is “Verification” in the Context of DO-254 (Avionics) Programs?
Functional Safety Mar 03, 2021 Article -
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A Formal Verification Technique for Complex Arithmetic Hardware
Formal Verification Mar 03, 2021 Article -
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The Six Steps Of RISC-V Processor Verification Including Vector Extensions
Verification IP Mar 03, 2021 Article
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November 2020
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Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs
Verification IP Oct 26, 2020 Article -
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Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver
Coverage Oct 26, 2020 Article -
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July 2020
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Formal Is The “New Normal” - Deploy These FV Apps In Your Next Project
Formal Verification Jul 19, 2020 Article -
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Bridging the Portability Gap for UVM SPI VIP Core Reuse From IP to Sub-System and SoC
UVM Jul 19, 2020 Article -
PCIe® Simulation Speed-Up with PLDA PCIe® Controller for DMA Application
Verification IP Jul 19, 2020 Article -
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Extending SoC Design Verification Methods for RISC-V Processor DV
Verification IP Jul 19, 2020 Article -
Effective Validation Method of Safety Mechanism Compliant with ISO 26262
Functional Safety Jul 19, 2020 Article
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March 2020
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Using Questa SLEC to Speed Up Verification of Multiple HDL Outputs
Formal Verification Mar 01, 2020 Article -
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An Open Data Management Tool for Design and Verification
Verification Management Mar 01, 2020 Article -
Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip
Verification IP Mar 01, 2020 Article -
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December 2019
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Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
Acceleration Dec 03, 2019 Article -
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Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
CDC Dec 03, 2019 Article
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June 2019
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SystemC FMU for Verification of Advanced Driver Assistance Systems
Functional Safety Jun 03, 2019 Article -
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UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
UVMF Jun 03, 2019 Article
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February 2019
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November 2018
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June 2018
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Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Standards Jun 29, 2018 Article -
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
Functional Safety Jun 29, 2018 Article -
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Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
Low Power Jun 29, 2018 Article -
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UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
Acceleration Jun 29, 2018 Article
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March 2018
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From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1
Low Power Mar 01, 2018 Article -
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A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
Verification IP Mar 01, 2018 Article
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November 2015
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February 2013
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Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
SystemVerilog Feb 22, 2013 Article -
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