Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Continuous Integration - March 28th
      • SystemVerilog Assertions
      • SoC Design & Functional Safety Flow
      • 2022 Functional Verification Study
      • Design Solutions as a Sleep Aid
      • CDC and RDC Assist
      • Formal and the Next Normal
      • Protocol and Memory Interface Verification
      • Webinar Calendar
    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
      • Formal Verification Made Easy
      • Fix FPGA Failures Faster
      • HPC Protocols & Memories
      • FPGA Design Challenges
      • High Defect Coverage
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Complex Safety Architectures
      • Data Independence and Non-Determinism
      • Hierarchical CDC+RDC
      • All On-Demand Recordings
    • Recording Archive

      • Aerospace & Defense Tech Day
      • Exhaustive Scoreboarding
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • Visualizer Debug Environment
      • Preparing for PCIe 6.0: Parts I & II
      • Automotive Functional Safety Forum
      • Siemens EDA Functional Verification
      • Improving Your SystemVerilog & UVM Skills
      • All Webinar Topics
    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
  • Home
  • Verification Horizons
  • March 2018 | Volume 14, Issue 1

March 2018 | Volume 14, Issue 1

Verification Horizons - Tom Fitzpatrick, Editor

Verification Horizons Complete Issue:

  • Download - 7.2 MB

Verification Horizons Articles:

Achieving Your Team Goals Is Similar to Winning a Super Bowl Championship

by Tom Fitzpatrick - Mentor, A Siemens Business

In preparing this issue of Verification Horizons, I was planning to write my Editor's Note, once again, about the Patriots winning the Super Bowl. I had it all worked out how I was going to write about the need for preparation, planning, and execution and how a long-established methodology can bring disparate pieces of a project together to meet requirements and achieve your team goals. It was going to be great.

And then the Patriots lost.

To be fair, as a former colleague of mine wrote to me after the game, it was the most impressive losing effort in Super Bowl history, but it was still a loss. With the Patriots driving for what would have been the winning touchdown in the closing minutes, the Eagles—for the first and only time in the game—got to Tom Brady and forced a fumble that effectively ended the game. From the perspective of a Patriots fan, it was the football equivalent of a bug escaping into production hardware: a disaster.


Make Your Constraints More Dynamic with Portable Stimulus

by Matthew Ballance - Mentor, A Siemens Business

If you work in functional verification, you've likely become quite familiar with random constraints from functional verification languages such as SystemVerilog. Using a constraint solver to automate stimulus generation is key to quickly generating lots of stimulus that hits cases that weren't envisioned by the test writer. When using constrained-random generation, constraints are the mechanism by which we customize what is legal and interesting in the stimulus space.

Accellera's Portable Stimulus Standard (PSS) introduces some new constraint capabilities, in addition to supporting the capabilities that we've become familiar with in SystemVerilog. This article provides a guided tour of one of these new constraint features, along with examples that highlight their benefits.

If you've used SystemVerilog, you're likely very familiar with the constraint construct; random constraints declared within a class along with random fields. When an instance of the class is randomized, the constraints limit the available range of values.

Configuring Memory Read Completions Sent by PCIe® QVIP

by Arushi Jain and Rajat Rastogi - Mentor, A Siemens Business

PCI Express® (PCIe) is a point-to-point serial transceiver interconnect that provides higher transfer rates, increased bandwidth, and, hence, higher performance than its precursors: PCI and PCI-X. Its basic topology consists of an active root complex (downstream port) and an active endpoint (upstream port) device, wherein root complex signifies the root of an I/O hierarchy that connects the processor/memory subsystem to an I/O.

To a large extent, PCIe uses memory and completion request layer packets (TLP) to communicate information between memory mapped devices (transmitter and receiver). Memory requests transfer data to and from a memory mapped location and are typically categorized into memory write and memory read requests. Memory read requests must be completed by the receiver, also known as the completer. The size of memory read requests are limited by the transmitter configuration setting, known as maximum read request size (MRS).

OOB signaling is responsible for initializing the SATA interface as well as recovery from low power states. Initialization is the process of synchronous handshaking using OOB signals between two connected physical units. An important aspect of initialization is the speed negotiation process, which helps in establishing a common data transfer speed between host and device for effective communication.

SATA Specification 3.3 Gaps Filled by SATA QVIP

by Naman Saxena, Nitish Goel, and Rajat Rastogi - Mentor, A Siemens Business

Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a highspeed
serial protocol with a point to point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.

Starting with SATA GEN1's data transfer speeds of 1.5 Gbps, the speed has gone up to 6 Gbps in SATA GEN3. The physical layer is responsible for transmitting and receiving serial data streams. It employs gigabit technology, 8b/10b encoding, and Out-Of-Band (OOB) signaling that forms the
essence of high-speed serial communication.

Part I: Power Aware Static Verification - From Power Intent to Microarchitectural Checks of Low-Power Designs

by Progyna Khondkar - Mentor, A Siemens Business

PA-Static verification, more popularly known as PAStatic checks, are performed on designs that adopt certain power dissipation reduction techniques through the power intent or UPF. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structure of the design. More precisely, the rule sets are applied on the physical structure, architecture, and microarchitecture of the design, in conjunction with the UPF specification but without the requirements of any external stimulus or testbenches.

PA-Static verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF). These power management MV cells are essential for powershutdown. The generic functionalities of these cells may be best summarized as follows.

SVA Alternative for Complex Assertions

by Ben Cohen, VHDLCohen Publishing

Assertion-based verification has been an integral part of modern-day design verification. Concurrent SVA is a powerful assertion language that expresses the definition of properties in a concise set of notations and rules; its use is very wide spread and is definitely encouraged. However, SVA is designed for a static world; it fails to easily address the use of delays and repetitions based on the values of unit variables (module, checker, interface); it cannot reference non-static class properties or methods; care should be taken when accessing large data structures, especially large dynamic data structures; sequence_ match_item cannot directly modify unit variables; there are very strict rules on how property local variables are processed in the ORing and ANDing of sequences, and the flow through of those variables. It is important to note that those restrictions should not be viewed as a discount of SVA because SVA easily addresses most common cases of chip design requirements. In addition, the alternative presented in this article is only applicable for simulation, but definitely not for formal verification, as that is only supported by assertion languages (SVA, PSL).

This article first explains the concepts, and then by example, how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multi-threading and exit of threads upon a condition, such as vacuity or an error in the assertion. The article then provides examples that demonstrate how some of the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit (but not vendor's implementations) of SVA. Another possibility to handle these issues is to use checker libraries such as OVL, Go2UVM2; those checkers are not addressed in this article. Again, it is important to emphasize that this alternate solution with tasks should only be used when those difficult situations arise.

A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs

by Arun Chandra and Mike Bartley, T&VS

RISC-V (pronounced "risk-five") is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on
architecture, paving the way for the next 50 years of computing design and innovation.

A RISC-V microprocessor can be configured in several architectural modes depending upon the target market and applications. Further, each microprocessor implementation can have different micro-architectural parameters depending upon performance, and power considerations. Examples of such micro-architectural parameters are cache sizes, the use of branch prediction, result forwarding, and pre-fetch to name a few.

This article outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs. A three-level (unit, core and SoC) hierarchy is proposed for testbenches. Each level of the hierarchical testbench is configurable for both architectural and micro-architectural parameters. At the heart of the verification strategy is an ISG (Instruction Stream Generator) and a UVM testbench. The ISG can be configured according to the RISC-V architecture and then constrained to verify micro-architectural features. The generation of the specific configurable UVM testbench is automated based on a configuration file. The checkers, active testbench items like injectors, and coverage objects, are mostly portable across the various hierarchical levels, and are configurable based on the configuration file.

← Back to Verification Horizons

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA