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INTRODUCTION
The world of ASIC and FPGA design has been adopting the Universal Verification Methodology (UVM [1]) over the last several years. UVM is a culmination of well-known ideas, thoughts and best practices. Though UVM-1.1d is the most popular and default UVM version, UVM-1.2 has been around for a few years and has been adopted by many leading-edge semiconductor design houses. The upcoming IEEE version of UVM (IEEE P1800.2) is set to make UVM even more widely adopted, just like many other IEEE standards.
While UVM is great in building testbenches and test scenarios/sequences, the primary objective of UVM was to build robust, reusable testbenches. For IP and sub-system level verification, these scenarios could be constrained-random
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