Questa Equivalent FPGA Retargeting Flow

The Questa™ Equivalent FPGA retargeting solution allows for system designs residing on obsolete Field Programmable Gate Arrays (FPGAs) to be retargeted
onto newer technology, extending the life of these designs while also taking advantage of the latest safety, security, and power saving features.

Many designs implemented on obsolete FPGAs are still functionally viable, but end-of-life supply limitations result in an inability to acquire additional parts. Alternatively, remaining supplies may have become cost prohibitive or present other supply chain risks (for example, counterfeit risk). The time, resources, and cost of redesign may also not be practical. Finally, modern FPGA technologies offer significant benefits that obsolete technologies do not have in terms of safety, security and trust, and power-saving features.

Retargeting these designs to newer FPGA technologies extends the life of designs and ensures that the designs are brought up to the latest safety and security standards while simultaneously reducing power consumption.

A retargeting solution has the unique ability to take the final netlist from the original design and generate a functionally equivalent final netlist in the modern target FPGA technology. Months of engineering time can be eliminated because
designers do not have to recreate the RTL for reimplementation on a modern FPGA device. The Questa Equivalent FPGA solution from Siemens EDA, a part of Siemens Digital Industries Software, provides retargeting technology alongside a step-by-step guide on how to precisely retarget the original final netlist.

This paper will describe three general retargeting approaches. This paper introduces:

• Overall methodology to retarget a netlist from an obsolete technology to a netlist in an advanced technology node
• Use Case 1: Equivalence with RTL, if available
• Use Case 2: RTL retargeting
• Use Case 3: RTL-RTL retargeting

^{Figure 1: Questa Equivalent FPGA retargeting flow}

Retargeting Flow

The technology is first applied to the original netlist to produce the retargeted netlist. The retargeted netlist is then re-synthesized using an FPGA implementation flow for the specified FPGA technology to create the final netlist for the new FPGA. The Questa Equivalent FPGA equivalence checking solution can be used to qualify the equivalence of all the steps used in the flow.