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• David Torres (author)
• Deadlock Prevention Made Easy with Formal Verification (Article)
• Deadlock Verification for Dummies: The Easy Way Using SVA and Formal (Paper)
• Deadlock Verification for Dummies: The Easy Way Using SVA and Formal (Webinar)
• Dealing With UVM and OVM Sequences (Article)
• Debug (topic)
• Debug Like a Pro: VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim (Webinar)
• Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses (Paper)
• Debugging Inconclusive Assertions and a Case Study (Article)
• Debugging Your Design in a Heterogeneous Environment (Conference)
• Defining an API (Chapter)
• Delivering First Silicon Success for Your Next SoC or 3DIC (Webinar)
• Democratizing Digital-Centric Mixed-Signal Verification Methodologies (Article)
• Dennis Brophy (author)
• Deploying HLS in a DO-254/ED-80 Workflow (Article)
• Deploying a Metrics Driven Low Power Methodology for Your RTL IP (Webinar)
• Deprecated Code (Chapter)
• Describing Low Power Logic with UPF (Session)
• Design Complexity Reduction (Session)
• Design Exploration with the Advanced Search Window (Demo)
• Design For Analysis (Chapter)
• Design Methodologies (Session)
• Design Patterns Examples (Lesson)
• Design Patterns and Parameterized Classes (Lesson)
• Design Topologies (Session)
• Design Trends (Session)
• Designing A Portable Stimulus Reuse Strategy (Article)
• Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip (Article)
• Developing "Safe" AI Hardware (Conference)
• Dharmendra Patel (author)
• Did You Know QuestaSim Supports VHDL-2019? (Webinar)
• Didan Francis (author)
• Digital Functional Verification for Safety-Critical Automotive Applications (Webinar)
• Digital Thread, Digital Twin, and IC Development (Article)
• Dinesh Tyagi (author)
• Direct Formal Property Checking: Improving Quality and Time-to-Market with Formal (Webinar)
• Do Not Forget to 'Cover' your SystemC Code with UVMC (Paper)
• Does Design Size Influence First Silicon Success? (Article)
• Dominic Lucido (author)
• Dominik Mentel (author)
• Don't Forget the Little Things That Can Make Verification Easier (Article)
• Don't Let VHDL Debugging Slow You Down! Use Questa One Sim (Webinar)
• Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon (Article)
• Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC (Webinar)
• Doug Smith (author)
• Dr. Abdelouahab Ayari (author)
• Dr. Ashish Darbari (author)
• Dr. Hans van der Schoot (author)
• Dr. Jeremy Levitt (author)
• Dr. Jonathan Graf (author)
• Dr. Mike Bartley (author)
• Driver Sequence API (Chapter)
• Driver and Receiving Tracing (Demo)
• Dual Top Architecture (Chapter)
• Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design Methodology (Seminar)
• Easy Solutions (Session)
• Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI (Paper)
• Easy Test Writing with a Proxy-driven Testbench (Webinar)
• Easy Testbench Evolution: Styling Sequences and Drivers (Paper)
• Easy Testbench Speedups (Article)
• Editor Insight (Session)
• Effective Elements List and Transitive Natures of UPF Commands (Paper)
• Effective Elements Lists and the Transitive Nature of UPF Commands (Article)
• Effective Identification of Reset Tree Bugs to Mitigate RDC Issues (Paper)
• Effective Resource Utilization in PCIe® Gen6: Shared Flow Control (Article)
• Effective Validation Method of Safety Mechanism Compliant with ISO 26262 (Article)
• Effectively Modeling and Analyzing Coverage (Webinar)
• Efficient Interconnect Formal Verification for Complex, Large-scale Designs (Webinar)
• Efficient Modeling Styles and Methodology for Gate-Level Design Verification (Paper)
• Ellie Burns (author)
• Elvin Serrao (author)
• Embedded Software Debug Using Codelink and Visualizer (Webinar)
• Emulation (Chapter)
• Emulation - A Job Management Strategy to Maximize Use (Article)
• Emulation Based Approach to ISO 26262 Compliant Processors Design (Article)
• Emulation-Ready Testbench Examples (Chapter)
• Enabling Formal Verification at Scale: An Agentic AI-driven Approach to RTL Bring-up (Conference)
• Enabling Model-Based Design for DO-254 Certification Compliance (Article)
• Enabling RISC-V Based System Development (Article)
• End of Test (Chapter)
• Enhanced Randomization and Functional Coverage: Make Better VHDL Testbenches (Conference)
• Enhanced Simulation Debugging through Advanced Capabilities of Visualizer (Conference)
• Enhancing Automotive Safety Verification Using Questa One Sim FX (Webinar)
• Enhancing Defect Coverage in Design for Testability (DFT) with Functional Fault Grading (Webinar)
• Enhancing PCIe Verification: How to Step Off the Map (Article)
• Enterprise Debug for Formal Verification (Webinar)
• Enterprise Debug for Simulation and Formal (Seminar)
• Enterprise Ethernet PHY Verification (Seminar)
• Enterprise Verification Debug and Analysis (Webinar)
• Environment Code Generation (Session)
• Environments: Architecture and Operation (Session)
• Equivalence Checking for FPGA (Webinar)
• Equivalence Validation of Analog Behavioral Models (Paper)
• Erich Marschner (author)
• Erik Jessen (author)
• Espen Tallaksen (author)
• Establishing a Company Wide Verification Reuse Library (Webinar)
• Evolution of Debug (Webinar)
• Evolution of UPF: Getting Better All the Time (Article)
• Evolving the Use of Formal Model Checking in SoC Design Verification (Article)