New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific


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    Authors: Amit Tanwar - Mentor GraphicsManoj Manu - Mentor Graphics Introduction: The common PHY found in PCI Express, USB 3.0 and 3.1, and SATA devices help accelerate development of these devices by implementing the physical layer functionality as a discrete IC or macro cell, which can easily be included in ASIC designs. In bus-based layered protocols, PHY typically provides the following functionality: Various serial data transmission rates8, 16, or 32-bit parallel interface to transmit and receive dataRecovery of data and clock from the serial streamHolding registers to stage transmit and receive dataDirect disparity control to transmit compliance patternsVarious encode/decode and error indicationsReceiver detectionBeacon transmission and receptionLow Frequency Periodic Signaling (LFPS) transmissionSelectable Tx margining, Tx de-emphasis, and signal swing valuesCOMINIT and COMRESET transmission and receptionMulti-lane de-skew A comprehensive PHY verification plan must verify all of the PHY functionality in various conditions. Verification IP needs to serve hundreds of configuration and may not fit well for comprehensive PHY verification. A PCI Express Verification IP in itself covers more than 500 configurations. This creates the need of an extended version of Verification IP which completely focus on PHY related aspects. In this paper, the PHY features are described in the context of PCI Express and USB protocols. However, in terms of the PHY verification methodology, this paper applies to all serial protocols that use a common PHY. View & Download: Login to view the Extending a Traditional VIP to Solve PHY Verification Challenges technical paper.